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CD14538BMSF PDF预览

CD14538BMSF

更新时间: 2024-11-11 14:48:23
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
9页 76K
描述
4000/14000/40000 SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP16, FRIT SEALED, CERAMIC, DIP-16

CD14538BMSF 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.17Is Samacsys:N
系列:4000/14000/40000JESD-30 代码:R-GDIP-T16
JESD-609代码:e0逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR
数据/时钟输入次数:1功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):810 ns
认证状态:Not Qualified座面最大高度:5.08 mm
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CD14538BMSF 数据手册

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CD14538BMS  
CMOS Dual Precision  
Monostable Multivibrator  
November 1994  
Features  
Description  
• High-Voltage Type (20V Rating)  
CD14538BMS dual precision monostable multivibrator provides stable retrigger-  
able/resettable one-shot operation for any fixed-voltage timing application.  
• Retriggerable/Resettable Capability  
• Trigger and Reset Propagation Delays Inde-  
pendent of RX, CX  
An external resistor (RX) and an external capacitor (CX) control the timing and  
accuracy for the circuit. Adjustment of RX and CX provides a wide range of out-  
put pulse widths from the Q and Q terminals. The time delay from trigger input to  
output transition (trigger propagation delay) and the time delay from reset input  
to output transition (reset propagation delay) are independent of RX and CX. Pre-  
cision control of output pulse widths is achieved through linear CMOS tech-  
niques.  
• Triggering From Leading or Trailing Edge  
• Q and Q Buffered Outputs Available  
• Separate Resets  
• Wide Range of Output-Pulse Widths  
• Schmitt-Trigger Input Allows Unlimited Rise  
and Fall Times On +TR and -TR Inputs  
Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) inputs are pro-  
vided for triggering from either edge of an input pulse. An unused +TR input  
should be tied to VSS. An unused -TR input should be tied to VDD. A RESET  
(on low level) is provided for immediate termination of the output pulse or to pre-  
vent output pulses when power is turned on. An unused RESET input should be  
tied to VDD. However, if an entire section of the CD14538BMS is not used, its  
inputs must be tied to either VDD or VSS. See Table 1.  
• 100% Tested For Maximum Quiescent Cur-  
rent at 20V  
• Maximum Input Current of 1µA at 18V Over  
Full Package-Temperature Range:  
- 100nA at 18V and +25oC  
• Noise Margin (Full Package-Temperature  
Range):  
In normal operation the circuit retriggers (extends the output pulse one period)  
on the application of each new trigger pulse. For operation in the non-retrigger-  
able mode, Q is connected to -TR when leading-edge triggering (+TR) is used  
or Q is connected to +TR when trailing-edge triggering (-TR) is used. The time  
period (T) for this multivibrator can be calculated by: T = RXCX.  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
The minimum value of external resistance, RX is 4K. The minimum and maxi-  
mum values of external capacitance, CX, are 0pF and 100µF, respectively.  
• 5V, 10V and 15V Parametric Ratings  
• Standardized Symmetrical Output Charac-  
teristics  
The CD14538BMS is interchangeable with type MC14538 and is similar to and  
pin-compatible with the CD4098B* and CD4538B**.  
• Meets All Requirements of JEDEC Tentative  
Standards No. 13B, “Standard Specifica-  
tions for Description of “B” Series CMOS  
Device’s  
* T = 0.5 R C for C 1000pF.  
X
X
X
* T = R C ; C min = 5000pF.  
X
X
X
The CD14538BMS is supplied in these 16-lead outline packages:  
Applications  
• Pulse Delay and Timing  
Braze Seal DIP  
Frit Seal DIP  
H4X  
H1L  
• Pulse Shaping  
Ceramic Flatpack H6W  
Pinout  
Functional Diagram  
CX1  
2
RX1  
CD14538BMS  
TOP VIEW  
VDD  
1
RXCX(1)  
6
CX1  
RXCX (1)  
RESET (1)  
+TR (1)  
-TR (1)  
Q1  
1
2
3
4
5
6
7
8
16 VDD  
+TR  
-TR  
4
5
3
Q1  
Q1  
15 CX2  
MONO1  
MONO2  
14 RXCX (2)  
13 RESET (2)  
12 +TR (2)  
11 -TR (2)  
10 Q2  
RESET  
7
+TR 12  
-TR 11  
10 Q2  
RESET 13  
9
Q2  
Q1  
9
Q2  
VSS  
15 14 RXCX(2)  
CX2 RX2  
VDD = 16  
VSS = 8  
VDD  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3192  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19979-640  

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