Datasheet > CD1284

CD1284

更新时间： 2024-11-28 21:55:23

品牌	Logo	应用领域
英特尔 - INTEL		控制器
页数	文件大小	规格书
176页	2107K
描述
IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

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CD1284 数据手册

CD1284

IEEE 1284-Compatible Parallel Interface Controller

with Two High-Speed Asynchronous Serial Ports

Datasheet

Product Features

Parallel Port (Peripheral-side)

Two Serial UARTs

■ Serial channel asynchronous protocol

support to 115.2 kbps (register-set-

compatible and functionally identical to

CD1400)

High-speed, bidirectional, multi-protocol

parallel port:

■ Hardware implementation of all modes of

the IEEE STD (Standard) 1284

specification (including automatic

negotiation)

—Twelve-byte FIFOs for each transmitter

and receiver with programmable

threshold for receive FIFO interrupt

generation

—Centronics -compatible mode

—Reverse Byte mode

—Improved interrupt schemes: Good

Data interrupts eliminate the need for

character status check

—Reverse Nibble mode

—ECP (extended capabilities port) mode

with run-length encoding/decoding

—User-programmable and automatic flow

control for serial channels

—EPP (enhanced parallel port) mode

—Special character recognition and

generation.

—Up to 2-Mbytes/sec. transfer rate in ECP

and EPP modes

—Special character processing,

particularly useful for UNIX

■ 64-byte parallel FIFO with DMA interface

environments, optionally handled

automatically by the serial channels.

—Six modem control signals per channel

(DTR, DSR, RTS, CTS, CD, and RI)

As of May 2001, this document replaces the Basis

Communications Corp. document.

May 2001

CL-CD1284 — IEEE 1284-Compatible Parallel Interface Controller

12 3 4 5 6 7...176

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