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CAY16-000F2LF PDF预览

CAY16-000F2LF

更新时间: 2024-11-24 03:13:03
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伯恩斯 - BOURNS /
页数 文件大小 规格书
4页 316K
描述
Chip Resistor Arrays

CAY16-000F2LF 数据手册

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Features  
Lead free version available (see How to Order “Termination” options)  
Lead free versions are RoHS compliant*  
Convex and concave terminals  
2, 4 or 8 isolated elements available  
Resistance tolerance 1 ꢀ and 5 ꢀ  
Resistance range: 10 ohms to 1 megohm  
CAT/CAY 16 Series - Chip Resistor Arrays  
Specifications  
Requirement  
Characteristics  
Test Method  
Short Time Overload  
Soldering Heat  
±± ꢀ ꢁ±( ꢀ %or ꢂT±6-F8, -J8 & ꢂꢃY±6-J8)  
Rated Voltage X (.5, 5 seconds  
(60 °ꢂ ±5 °ꢂ, ±0 seconds ±± second  
±± ꢀ  
±± ꢀ  
Temperature ꢂycling ꢁ5)  
±(5 °ꢂ ꢁ30 minutes) - normal ꢁ±5 minutes)  
-30 °ꢂ ꢁ30 minutes) - normal ꢁ±5 minutes)  
Moisture Load Li%e  
Load Li%e  
±( ꢀ ꢁ±3 ꢀ %or ꢂT±6-F8, -J8 & ꢂꢃY±6-J8)  
±( ꢀ ꢁ±3 ꢀ %or ꢂT±6-F8, -J8 & ꢂꢃY±6-J8)  
±000 hours  
±000 hours  
How To Order  
Characteristics  
CA Y 16 - 103 J 4 __  
ꢂhip ꢃrrays  
Characteristics  
CAT16/CAY16  
( ꢁJ(), 4 ꢁF4, J4), 8 ꢁF8, J8)  
6( mW ꢁ3± mW %or ꢂꢃY±6-J8)  
±± ꢀ, ±5 ꢀ  
Number o% Elements  
Power Rating Per Resistor  
Resistance Tolerance  
Type  
• T = ꢂoncave  
• Y = ꢂonvex  
Models  
• J( = 0606 Package Size  
• F4, J4 = ±(06 Package Size  
• F8 = (406 Package Size %or ꢂT±6  
• J8 = (406 Package Size %or ꢂT±6;  
±506 Package Size %or ꢂꢃY±6  
Resistance Range: E(4 ꢁJ), E96 + E(4 ꢁF)  
Zero-Ohm Jumper < 0.05 ohm  
±0 ohms - ± megohm  
Max. Working Voltage  
Operating Temp. Range  
50 V ꢁ(5 V %or ꢂꢃY±6-J8)  
-55 °ꢂ - ±(5 °ꢂ  
Resistance ꢂode  
• ±03 = ±0 K ohms  
• ±003 = ±00 K ohms ꢁ± ꢀ tolerance)  
• 000 = Zero-ohm  
Resistance Tolerance  
• J = ±5 ꢀ ꢁꢄse ꢅJꢆ %or zero-ohm jumper)  
• F = ±± ꢀ ꢁ4 resistor package and ꢂT±6-F8)  
Soldering Profile for Lead Free Chip Resistors and Arrays  
Resistors  
275  
<1>  
• ( = ( Isolated Resistors  
• 4 = 4 Isolated Resistors  
• 8 = 8 Isolated Resistors  
Maximum of 20 seconds between  
+255 °C and +260 °C  
260 °C peak  
<1>  
255 °C  
Terminations*  
225  
175  
125  
75  
• LF = Tin-plated ꢁlead %ree)  
• Blank = Solder-plated  
220 °C  
190 °C  
60 - 90  
seconds  
*Model ꢂꢃY±6-J8 is available only with tin-plated  
terminations.  
Ramp Down  
3 °C/second  
150 °C  
For Standard Values ꢄsed in ꢂapacitors,  
Inductors, and Resistors, click here.  
60 - 120 seconds  
10 seconds minimum  
Ramp Up  
3 °C/second maximum  
Schematics  
CAT16-J2  
CAY16-J2  
CAT16-F4, -J4  
CAY16-F4, -J4  
25  
0
50  
100  
150  
Time (seconds)  
200  
250  
300  
R
1
R
2
R
3
R
4
R
R
2
1
CAT16-F8, -J8  
CAY16-J8  
R
R
R
R
4
R
5
R
6
R
7
R
8
1
2
3
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex  
Specifications are subject to change without notice.  
Customers should verify actual device performance in their specific applications.  

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