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CAT5221YI-10TE13 PDF预览

CAT5221YI-10TE13

更新时间: 2024-11-22 22:10:43
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CATALYST /
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16页 114K
描述
Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface

CAT5221YI-10TE13 数据手册

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E
CAT5221  
Dual Digitally Programmable Potentiometers (DPP™)  
with 64 Taps and 2-wire Interface  
TM  
FEATURES  
Automatic recall of saved wiper settings at  
Two linear-taper digitally programmable  
power up  
potentiometers  
2.5 to 6.0 volt operation  
64 resistor taps per potentiometer  
Standby current less than 1µA  
1,000,000 nonvolatile WRITE cycles  
100 year nonvolatile memory data retention  
20-lead SOIC and TSSOP packages  
Industrial temperature ranges  
End to end resistance 2.5k, 10k, 50kor 100kΩ  
Potentiometer control and memory access via  
2-wire interface (I2C like)  
Low wiper resistance, typically 80  
Nonvolatile memory storage for up to four wiper  
settings for each potentiometer  
DESCRIPTION  
wiper control register or any of the non-volatile data  
registers is via a 2-wire serial bus (I2C-like). On power-  
up, the contents of the first data register (DR0) for each  
ofthefourpotentiometersisautomaticallyloadedintoits  
respective wiper control register (WCR).  
The CAT5221 is two Digitally Programmable  
Potentiometers (DPPs™) integrated with control logic  
and 16 bytes of NVRAM memory. Each DPP consists of  
aseriesof63resistiveelementsconnectedbetweentwo  
externallyaccessibleendpoints.Thetappointsbetween  
eachresistiveelementareconnectedtothewiperoutputs  
with CMOS switches. A separate 6-bit control register  
(WCR)independentlycontrolsthewipertapswitchesfor  
each DPP. Associated with each wiper control register  
are four 6-bit non-volatile memory data registers (DR)  
used for storing up to four wiper settings. Writing to the  
The CAT5221 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
R
H0  
R
H1  
SOIC Package (J, W)  
TSSOP Package (U, Y)  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
CC  
R
1
2
3
4
5
6
7
8
9
10  
W0  
WIPER  
CONTROL  
REGISTERS  
SCL  
SDA  
2-WIRE BUS  
INTERFACE  
NC  
NC  
NC  
R
L0  
R
H0  
R
R
W0  
W1  
A
A
0
2
A
1
CAT  
5221  
A
3
R
W1  
A0  
A1  
A2  
A3  
NONVOLATILE  
DATA  
REGISTERS  
CONTROL  
LOGIC  
SCL  
NC  
NC  
NC  
R
L1  
RH  
1
SDA  
GND  
R
R
L1  
L0  
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Document No. 2113, Rev. I  
1

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