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CAT5221YI-50-T2 PDF预览

CAT5221YI-50-T2

更新时间: 2024-11-23 11:54:19
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安森美 - ONSEMI 转换器电阻器光电二极管
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16页 226K
描述
Dual Digitally Programmable Potentiometer (DPP™) with 64 Taps and I2C Interface

CAT5221YI-50-T2 数据手册

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CAT5221  
Dual Digitally Programmable Potentiometer (DPP™) with  
64 Taps and I2C Interface  
FEATURES  
DESCRIPTION  
„ Two linear-taper digitally programmable  
The CAT5221 is two Digitally Programmable  
Potentiometers (DPPs™) integrated with control logic  
and 16 bytes of NVRAM memory. Each DPP consists  
of a series of 63 resistive elements connected  
between two externally accessible end points. The tap  
points between each resistive element are connected  
to the wiper outputs with CMOS switches. A separate  
6-bit control register (WCR) independently controls  
the wiper tap switches for each DPP. Associated with  
each wiper control register are four 6-bit non-volatile  
memory data registers (DR) used for storing up to four  
wiper settings. Writing to the wiper control register or  
any of the non-volatile data registers is via a I2C serial  
bus. On power-up, the contents of the first data  
register (DR0) for each of the four potentiometers is  
automatically loaded into its respective wiper control  
register (WCR).  
potentiometers  
„ 64 resistor taps per potentiometer  
„ End to end resistance 2.5 k, 10 k, 50 kor  
100 kΩ  
„ Potentiometer control and memory access via  
I2C interface  
„ Low wiper resistance, typically 80 Ω  
„ Nonvolatile memory storage for up to four  
wiper settings for each potentiometer  
„ Automatic recall of saved wiper settings at  
power up  
„ 2.5 to 6.0 volt operation  
„ Standby current less than 1µA  
„ 1,000,000 nonvolatile WRITE cycles  
„ 100 year nonvolatile memory data retention  
„ 20-lead SOIC and TSSOP packages  
„ Industrial temperature range  
The CAT5221 can be used as a potentiometer or as a  
two terminal, variable resistor. It is intended for circuit  
level or system level adjustments in a wide variety of  
applications.  
For Ordering Information details, see page 15.  
PIN CONFIGURATION  
FUNCTIONAL DIAGRAM  
SOIC 20 Lead (W)  
TSSOP 20 Lead (Y)  
R
R
H1  
H0  
RW0  
RL0  
1
2
3
4
5
6
7
8
9
20 VCC  
19 NC  
18 NC  
17 NC  
16 A1  
15 A3  
14 SCL  
13 NC  
12 NC  
11 NC  
SCL  
SDA  
WIPER  
CONTROL  
REGISTERS  
2
I C  
INTERFACE  
RH0  
A0  
R
R
W0  
W1  
A2  
CAT  
5221  
RW1  
RL1  
A0  
A1  
A2  
NONVOLATILE  
DATA  
REGISTERS  
CONTROL  
LOGIC  
RH1  
SDA  
A3  
GND 10  
R
R
L1  
L0  
© 2009 SCILLC. All rights reserved.  
Characteristics subject to change without notice  
1
Doc. No. MD-2113 Rev. M  

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