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CAT25C64SI-1.8TE13 PDF预览

CAT25C64SI-1.8TE13

更新时间: 2024-12-01 21:17:07
品牌 Logo 应用领域
安森美 - ONSEMI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
11页 403K
描述
CAT25C64SI-1.8TE13

CAT25C64SI-1.8TE13 技术参数

生命周期:Obsolete包装说明:SOIC-8
Reach Compliance Code:unknown风险等级:5.82
Is Samacsys:N最大时钟频率 (fCLK):1 MHz
JESD-30 代码:R-PDSO-G8内存密度:65536 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:8192 words字数代码:8000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL串行总线类型:SPI
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子位置:DUAL
最长写入周期时间 (tWC):10 msBase Number Matches:1

CAT25C64SI-1.8TE13 数据手册

 浏览型号CAT25C64SI-1.8TE13的Datasheet PDF文件第2页浏览型号CAT25C64SI-1.8TE13的Datasheet PDF文件第3页浏览型号CAT25C64SI-1.8TE13的Datasheet PDF文件第4页浏览型号CAT25C64SI-1.8TE13的Datasheet PDF文件第5页浏览型号CAT25C64SI-1.8TE13的Datasheet PDF文件第6页浏览型号CAT25C64SI-1.8TE13的Datasheet PDF文件第7页 
CAT25C32/64  
32K/64K-Bit SPI Serial CMOS EEPROM  
FEATURES  
1,000,000 program/erase cycles  
100 year data tetention  
10 MHz SPI compatible  
1.8 to 6.0 volt operation  
Hardware and software protection  
Low power CMOS technology  
SPI modes (0,0 &1,1)  
Self-timed write cycle  
8-pin DIP/SOIC and 14-pin TSSOP  
64-Byte page write buffer  
Block write protection  
Commercial, industrial and automotive  
– Protect 1/4, 1/2 or all of EEPROM array  
temperature ranges  
DESCRIPTION  
required to access the device. The HOLD pin may be  
used to suspend any serial communication without  
resetting the serial sequence. The CAT25C32/64 is  
designed with software and hardware write protection  
features including Block write protection. The device is  
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and  
20-pin TSSOP packages.  
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS  
EEPROM internally organized as 4Kx8/8Kx8 bits.  
Catalyst’s advanced CMOS Technology substantially  
reduces device power requirements. The CAT25C32/  
64 features a 64-byte page write buffer. The device  
operates via the SPI bus serial interface and is enabled  
thoughaChipSelect(CS). InadditiontotheChipSelect,  
the clock input (SCK), data in (SI) and data out (SO) are  
PIN CONFIGURATION  
DIP Package (P, L, GL)  
SOIC Package (S, V, GV)  
TSSOP Package (U14, Y14)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
8
VCC  
HOLD  
NC  
NC  
NC  
V
CS  
SO  
WP  
CS  
SO  
NC  
NC  
NC  
WP  
CS  
SO  
CC  
CC  
HOLD  
SCK  
SI  
HOLD  
SCK  
SI  
WP  
V
V
SS  
SS  
SCK  
SI  
V
SS  
BLOCK DIAGRAM  
SENSE AMPS  
SHIFT REGISTERS  
PIN FUNCTIONS  
COLUMN  
DECODERS  
WORD ADDRESS  
BUFFERS  
Pin Name  
Function  
SO  
Serial Data Output  
Serial Clock  
SO  
SI  
I/O  
CONTROL  
SCK  
WP  
VCC  
VSS  
CS  
E2PROM  
ARRAY  
CS  
SPI  
CONTROL  
LOGIC  
XDEC  
Write Protect  
WP  
HOLD  
SCK  
+1.8V to +6.0V Power Supply  
Ground  
BLOCK  
PROTECT  
LOGIC  
Chip Select  
DATA IN  
STORAGE  
SI  
Serial Data Input  
Suspends Serial Input  
HOLD  
HIGH VOLTAGE/  
TIMING CONTROL  
NC  
No Connect  
STATUS  
REGISTER  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1001, Rev. J  
1

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