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CAT25C64U14ATE13

更新时间: 2024-11-22 23:39:43
品牌 Logo 应用领域
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页数 文件大小 规格书
10页 58K
描述
SPI Serial EEPROM

CAT25C64U14ATE13 数据手册

 浏览型号CAT25C64U14ATE13的Datasheet PDF文件第2页浏览型号CAT25C64U14ATE13的Datasheet PDF文件第3页浏览型号CAT25C64U14ATE13的Datasheet PDF文件第4页浏览型号CAT25C64U14ATE13的Datasheet PDF文件第5页浏览型号CAT25C64U14ATE13的Datasheet PDF文件第6页浏览型号CAT25C64U14ATE13的Datasheet PDF文件第7页 
CAT25C32/64  
32K/64K-Bit SPI Serial CMOS EEPROM  
FEATURES  
1,000,000 program/erase cycles  
100 year data tetention  
Self-timed write cycle  
10 MHz SPI compatible  
1.8 to 6.0 volt operation  
Hardware and software protection  
Zero standby current  
8-pin DIP/SOIC, 14-pin TSSOP and 20-pin  
TSSOP  
Low power CMOS technology  
SPI modes (0,0 &1,1)  
64-Byte page write buffer  
Block write protection  
Commercial, industrial and automotive  
– Protect 1/4, 1/2 or all of EEPROM array  
temperature ranges  
DESCRIPTION  
required to access the device. The HOLD pin may be  
used to suspend any serial communication without  
resetting the serial sequence. The CAT25C32/64 is  
designed with software and hardware write protection  
features including Block write protection. The device is  
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and  
20-pin TSSOP packages.  
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS  
EEPROM internally organized as 4Kx8/8Kx8 bits.  
Catalyst’s advanced CMOS Technology substantially  
reduces device power requirements. The CAT25C32/  
64 features a 64-byte page write buffer. The device  
operates via the SPI bus serial interface and is enabled  
thoughaChipSelect(CS). InadditiontotheChipSelect,  
the clock input (SCK), data in (SI) and data out (SO) are  
BLOCK DIAGRAM  
PIN CONFIGURATION  
SOIC Package (S) TSSOP Package (U14) TSSOP Package (U20)  
14  
13  
12  
11  
10  
9
8
1
2
3
4
5
6
7
VCC  
HOLD  
NC  
NC  
NC  
CS  
SO  
NC  
NC  
NC  
WP  
1
2
3
4
8
7
6
5
1
SENSE AMPS  
SHIFT REGISTERS  
V
NC  
NC  
CS  
SO  
SO  
NC  
NC  
WP  
SS  
NC  
NC  
20  
19  
18  
17  
16  
15  
CS  
SO  
WP  
CC  
VCC  
HOLD  
HOLD  
NC  
2
HOLD  
SCK  
SI  
3
4
V
5
SS  
COLUMN  
DECODERS  
WORD ADDRESS  
BUFFERS  
SCK  
SI  
6
NC  
V
SS  
7
14 SCK  
13 SI  
12 NC  
11 NC  
V
8
DIP Package (P)  
9
SO  
SI  
I/O  
CONTROL  
10  
1
2
3
4
8
7
6
5
V
CS  
SO  
CC  
HOLD  
SCK  
SI  
E2PROM  
ARRAY  
CS  
SPI  
XDEC  
WP  
WP  
CONTROL  
LOGIC  
V
SS  
HOLD  
SCK  
PIN FUNCTIONS  
Pin Name  
BLOCK  
PROTECT  
LOGIC  
Function  
DATA IN  
STORAGE  
SO  
Serial Data Output  
Serial Clock  
SCK  
WP  
VCC  
VSS  
CS  
HIGH VOLTAGE/  
TIMING CONTROL  
Write Protect  
STATUS  
REGISTER  
+1.8V to +6.0V Power Supply  
Ground  
Chip Select  
SI  
Serial Data Input  
Suspends Serial Input  
HOLD  
NC  
No Connect  
© 2001 by Catalyst Semiconductor, Inc.  
Doc No. 1001, Rev. A  
Characteristics subject to change without notice  

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