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CAT24WC05UE-1.8REV-A PDF预览

CAT24WC05UE-1.8REV-A

更新时间: 2024-11-17 14:41:19
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
14页 361K
描述
EEPROM, 512X8, Serial, CMOS, PDSO8, MO-153AA, TSSOP-8

CAT24WC05UE-1.8REV-A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.92最大时钟频率 (fCLK):0.1 MHz
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.4 mm内存密度:4096 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:512 words字数代码:512
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:512X8
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
串行总线类型:I2C最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

CAT24WC05UE-1.8REV-A 数据手册

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CAT24WC03/05  
2K/4K-Bit Serial EEPROM with Partial Array Write Protection  
FEATURES  
Self-timed write cycle with auto-clear  
400 kHz I2C bus compatible*  
1.8 to 5.5 volt operation  
1,000,000 Program/Erase cycles  
100 Year data retention  
Low power CMOS technology  
8-pin DIP, 8-pin SOIC, 8-lead MSOP and 8-pin  
TSSOP Package  
Write protect feature  
–Top 1/2 array protected when WP at VIH  
Commercial, industrial and automotive  
temperature ranges  
16-Byte page write buffer  
"Green" package options available  
DESCRIPTION  
The CAT24WC03/05 is a 2K/4K-bit Serial CMOS  
EEPROM internally organized as 256/512 words of 8  
bits each. Catalyst’s advanced CMOS technology sub-  
stantially reduces device power requirements. The  
CAT24WC03/05 features a 16-byte page write buffer.  
The device operates via the I2C bus serial interface, has  
a special write protection feature, and is available in 8-  
pin DIP or 8-pin SOIC packages.  
PIN CONFIGURATION  
BLOCK DIAGRAM  
DIP Package (P, L, GL)  
SOIC Package (J, W, GW)  
EXTERNAL LOAD  
SENSE AMPS  
SHIFT REGISTERS  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
D
0
1
2
CC  
0
1
2
V
CC  
WP  
OUT  
WP  
ACK  
SCL  
SDA  
SCL  
SDA  
V
V
CC  
SS  
V
V
SS  
SS  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
MSOP Package (R, Z, GZ)  
TSSOP Package (U, Y, GY)  
START/STOP  
SDA  
WP  
1
2
3
4
8
7
6
5
A
A
A
1
2
3
4
8
7
6
5
0
1
2
V
CC  
WP  
A
A
A
0
1
2
V
CC  
WP  
LOGIC  
SCL  
SDA  
SCL  
SDA  
V
E2PROM  
SS  
V
XDEC  
SS  
CONTROL  
LOGIC  
PIN FUNCTIONS  
Pin Name  
Function  
DATA IN STORAGE  
A0, A1, A2  
SDA  
Device Address Inputs  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
SCL  
WP  
Write Protect  
SCL  
STATE COUNTERS  
VCC  
+1.8V to +5.5V Power Supply  
Ground  
SLAVE  
ADDRESS  
COMPARATORS  
A
A1  
A2  
0
VSS  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1005, Rev. F  
1

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