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CAT24WC05U-TE13REV-A PDF预览

CAT24WC05U-TE13REV-A

更新时间: 2024-11-19 13:06:39
品牌 Logo 应用领域
CATALYST 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
8页 46K
描述
EEPROM, 512X8, Serial, CMOS, PDSO8, MO-153AA, TSSOP-8

CAT24WC05U-TE13REV-A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.92最大时钟频率 (fCLK):0.1 MHz
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.4 mm内存密度:4096 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:512 words字数代码:512
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512X8
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
串行总线类型:I2C最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

CAT24WC05U-TE13REV-A 数据手册

 浏览型号CAT24WC05U-TE13REV-A的Datasheet PDF文件第2页浏览型号CAT24WC05U-TE13REV-A的Datasheet PDF文件第3页浏览型号CAT24WC05U-TE13REV-A的Datasheet PDF文件第4页浏览型号CAT24WC05U-TE13REV-A的Datasheet PDF文件第5页浏览型号CAT24WC05U-TE13REV-A的Datasheet PDF文件第6页浏览型号CAT24WC05U-TE13REV-A的Datasheet PDF文件第7页 
Preliminary  
CAT24WC03/05/09/17  
2K/4K/8K/16K-Bit Serial E2PROM  
FEATURES  
400 KHZ I2C Bus Compatible*  
1.8 to 6.0Volt Operation  
Self-Timed Write Cycle with Auto-Clear  
1,000,000 Program/Erase Cycles  
100 Year Data Retention  
Low Power CMOS Technology  
8-pin DIP, 8-pin SOIC and 8-pin TSSOP Package  
Write Protect Feature  
–Top 1/2 Array Protected When WP at VIH  
Commercial, Industrial and Automotive  
Temperature Ranges  
16-Byte Page Write Buffer  
DESCRIPTION  
ments. The CAT24WC03/05/09/17 features a 16-byte  
page write buffer. The device operates via the I2C bus  
serial interface, has a special write protection feature,  
and is available in 8-pin DIP or 8-pin SOIC  
TheCAT24WC03/05/09/17isa2K/4K/8K/16K-bitSerial  
CMOS E2PROM internally organized as 256/512/1024/  
2048 words of 8 bits each. Catalyst’s advanced CMOS  
technology substantially reduces device power require-  
PIN CONFIGURATION  
BLOCK DIAGRAM  
EXTERNAL LOAD  
DIP Package (P)  
SOIC Package (J)  
SENSE AMPS  
SHIFT REGISTERS  
D
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
OUT  
A
A
A
V
A
A
A
0
1
2
CC  
0
1
2
V
CC  
WP  
ACK  
WP  
V
SCL  
SDA  
CC  
SCL  
SDA  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
V
V
SS  
SS  
V
SS  
START/STOP  
TSSOP Package (U)  
SDA  
WP  
(** Available for 24WC03 only)  
LOGIC  
1
2
3
4
8
7
6
5
A
A
A
0
1
2
V
CC  
WP  
E2PROM  
SS  
XDEC  
SCL  
SDA  
CONTROL  
LOGIC  
V
SS  
PIN FUNCTIONS  
DATA IN STORAGE  
Pin Name  
Function  
A0, A1, A2  
SDA  
Device Address Inputs  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
SCL  
SCL  
STATE COUNTERS  
WP  
Write Protect  
SLAVE  
ADDRESS  
COMPARATORS  
A
A1  
A2  
0
VCC  
+1.8V to +6.0V Power Supply  
Ground  
VSS  
24WCXX F03  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© 1999 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25063-00 2/98 S-1  
1

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