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CAT24WC01R-TE13REV-F PDF预览

CAT24WC01R-TE13REV-F

更新时间: 2024-11-06 19:04:51
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器双倍数据速率光电二极管内存集成电路
页数 文件大小 规格书
14页 1126K
描述
EEPROM, 128X8, Serial, CMOS, PDSO8, MO-187AA, MSOP-8

CAT24WC01R-TE13REV-F 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP,
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.71最大时钟频率 (fCLK):0.1 MHz
JESD-30 代码:S-PDSO-G8JESD-609代码:e0
长度:3 mm内存密度:1024 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:128 words字数代码:128
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128X8
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.1 mm
串行总线类型:I2C最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

CAT24WC01R-TE13REV-F 数据手册

 浏览型号CAT24WC01R-TE13REV-F的Datasheet PDF文件第2页浏览型号CAT24WC01R-TE13REV-F的Datasheet PDF文件第3页浏览型号CAT24WC01R-TE13REV-F的Datasheet PDF文件第4页浏览型号CAT24WC01R-TE13REV-F的Datasheet PDF文件第5页浏览型号CAT24WC01R-TE13REV-F的Datasheet PDF文件第6页浏览型号CAT24WC01R-TE13REV-F的Datasheet PDF文件第7页 
Not Recommended for New Design,  
Replace with CAT24C16  
CAT24WC01/02/04/08/16  
1K/2K/4K/8K/16K-Bit Serial EEPROM  
FEATURES  
Self-Timed Write Cycle with Auto-Clear  
1,000,000 Program/Erase Cycles  
100 Year Data Retention  
400 kHz I2C Bus Compatible*  
1.8 to 5.5Volt Operation  
Low Power CMOS Technology  
8-pin DIP, SOIC, TSSOP and MSOP packages  
- "Green" package option available  
Write Protect Feature  
— Entire Array Protected When WP at VIH  
Commercial, Industrial, Automotive and  
Page Write Buffer  
Extended Temperature Ranges  
DESCRIPTION  
08/16 feature a 16-byte page write buffer. The device  
operates via the I2C bus serial interface, has a special  
write protection feature, and is available in 8-pin DIP,  
SOIC, TSSOP and MSOP packages.  
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-  
bit Serial CMOS EEPROM internally organized as 128/  
256/512/1024/2048 words of 8 bits each. Catalyst’s  
advanced CMOS technology substantially reduces de-  
vice power requirements. The the CAT24WC01/02/04/  
PIN CONFIGURATION  
DIP Package (P, L, GL)  
BLOCK DIAGRAM  
SOIC Package (J, W, GW)  
EXTERNAL LOAD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
0
1
2
CC  
0
1
2
V
CC  
WP  
SENSE AMPS  
SHIFT REGISTERS  
D
OUT  
WP  
ACK  
SCL  
SDA  
SCL  
SDA  
V
V
V
SS  
CC  
SS  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
V
SS  
5020 FHD F01  
TSSOP Package (U, Y, GY)  
START/STOP  
(MSOP and TSSOP available for CAT24WC01,  
CAT24WC02 and CAT24WC04 only)  
MSOP Package (R, Z, GZ)  
SDA  
WP  
LOGIC  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
A0  
A1  
A2  
A
A
A
CC  
0
1
2
V
CC  
WP  
WP  
E2PROM  
XDEC  
SCL  
SDA  
SCL  
SDA  
CONTROL  
LOGIC  
V
V
SS  
SS  
PIN FUNCTIONS  
DATA IN STORAGE  
Pin Name  
Function  
A0, A1, A2  
SDA  
Device Address Inputs  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
SCL  
SCL  
STATE COUNTERS  
WP  
Write Protect  
SLAVE  
ADDRESS  
COMPARATORS  
A
0
A1  
A2  
VCC  
+1.8V to +5.5V Power Supply  
Ground  
VSS  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. N  
1

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