Datasheet > CAT24C208YE-1.8

CAT24C208YE-1.8

更新时间： 2024-11-24 09:04:31

品牌	Logo	应用领域
CATALYST		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
14页	124K
描述
EEPROM

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中文翻译

获取价格

技术参数
数据手册

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CAT24C208YE-1.8 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

CAT24C208YE-1.8 数据手册

Advance Information

CAT24C208

8K (1K x 8) -Bit Dual Port Serial EEPROM for VESA Plug and Play Applications

in LCD Projectors and Monitors

FEATURES

■ 400 kHz I²C bus compatible*

■ 1,000,000 program/erase cycles

■ 100 year data retention

■ Complies with VESA E-EDID, E-DDC, DI-EXT

and M1 specifications

■ 8-pin DIP, SOIC, TSSOP or MSOP packages

- Green package option

■ 1.8 to 5.5 volt operation

■ Industrial and extended temperature ranges

■ Low power CMOS technology

■ 16-byte page write buffer

■ Self-timed write cycle with auto-clear

DESCRIPTION

Using Catalyst's advanced CMOS technology which

substantially reduces device power requirements, the

CAT24C208 can be powered from either of two

independent V_CCinputs.

The CAT24C208 is an 8k-bit Dual Port Serial CMOS

EEPROM internally organized as 1k words of 8 bits

each. The CAT24C208 features a 16-byte page write

buffer and can be accessed from either of two separate

I2C compatible ports, DSP (SDA, SCL) and DDC (SDA,

SCL) which conform to the VESA E-EDID EEPROM

Standard.

The CAT24C208 operates over the full industrial and

extended temperature range and is available in

miniature 8-pin DIP, SOIC, TSSOP and MSOP

packages.

Arbitration between the two interface ports is automatic

and allows the appearance of simultaneous access to

the memory from both interfaces.

BLOCK DIAGRAM

DSP VCC

DDC VCC

ARBITRATION

LOGIC

1K X 8

MEMORY

ARRAY

DDC

CONTROL

LOGIC

DISPLAY

CONTROL

LOGIC

DSP SCL

DSP SDA

DDC SCL

DDC SDA

CONFIGURATION

DDC SEL

VSS

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.

Characteristics subject to change without notice

Doc. No. 1044, Rev. B

12 3 4 5 6 7...14

中文翻译

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