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CAT24C082PI-45 PDF预览

CAT24C082PI-45

更新时间： 2024-01-25 13:38:48
品牌 Logo 应用领域
CATALYST 光电二极管外围集成电路
页数 文件大小 规格书
12页 71K
描述
Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

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CAT24C082PI-45 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP,
针数：8Reach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.92
JESD-30 代码：R-PDIP-T8JESD-609代码：e0
长度：9.27 mm端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified座面最大高度：4.57 mm
最大供电电压：6 V最小供电电压：2.7 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

CAT24C082PI-45 数据手册

 浏览型号CAT24C082PI-45的Datasheet PDF文件第5页浏览型号CAT24C082PI-45的Datasheet PDF文件第6页浏览型号CAT24C082PI-45的Datasheet PDF文件第7页浏览型号CAT24C082PI-45的Datasheet PDF文件第9页浏览型号CAT24C082PI-45的Datasheet PDF文件第10页浏览型号CAT24C082PI-45的Datasheet PDF文件第11页 
CAT24CXX1/XX2  
ACKNOWLEDGE  
pointers of the CAT24CXXX. After receiving another  
acknowledgefromtheSlave,theMasterdevicetransmits  
thedatatobewrittenintotheaddressedmemorylocation.  
The CAT24CXXX acknowledges once more and the  
Master generates the STOP condition. At this time, the  
device begins an internal programming cycle to non-  
volatilememory.Whilethecycleisinprogress,thedevice  
will not respond to any request from the Master device.  
After a successful data transfer, each receiving device  
is required to generate an acknowledge. The  
acknowledging device pulls down the SDA line during  
the ninth clock cycle, signaling that it received the 8 bits  
of data.  
The CAT24CXXX responds with an acknowledge after  
receivingaSTARTconditionanditsslaveaddress.Ifthe  
device has been selected along with a write operation,  
it responds with an acknowledge after receiving each 8-  
bit byte.  
Page Write  
The CAT24CXXX writes up to 16 bytes of data in a single  
write cycle, using the Page Write operation. The page  
write operation is initiated in the same manner as the byte  
write operation, however instead of terminating after the  
initial byte is transmitted, the Master is allowed to send up  
to 15 additional bytes. After each byte has been  
transmitted, the CAT24CXXX will respond with an  
acknowledge and internally increment the lower order  
addressbitsbyone.Thehighorderbitsremainunchanged.  
WhentheCAT24CXXXbeginsaREADmodeittransmits  
8 bits of data, releases the SDA line and monitors the  
line for an acknowledge. Once it receives this  
acknowledge, the CAT24CXXX will continue to transmit  
data.IfnoacknowledgeissentbytheMaster,thedevice  
terminates data transmission and waits for a STOP  
condition.  
WRITE OPERATIONS  
IftheMastertransmitsmorethan16bytesbeforesending  
the STOP condition, the address counter ‘wraps around,’  
and previously transmitted data will be overwritten.  
Byte Write  
In the Byte Write mode, the Master device sends the  
START condition and the slave address information  
(with the R/W bit set to zero) to the Slave device. After  
the Slave generates an acknowledge, the Master sends  
a 8-bit address that is to be written into the address  
When all 16 bytes are received, and the STOP condition  
has been sent by the Master, the internal programming  
cycle begins. At this point, all received data is written to  
the CAT24CXXX in a single write cycle.  
Figure 7. Byte Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS  
DATA  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
DATA n  
DATA n+1  
DATA n+15  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc. No. 3000, Rev. A  
8
1...56789101112

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