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CAT24C022PA-45 PDF预览

CAT24C022PA-45

更新时间: 2023-06-15 00:00:00
品牌 Logo 应用领域
CATALYST 光电二极管
页数 文件大小 规格书
12页 71K
描述
Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

CAT24C022PA-45 数据手册

 浏览型号CAT24C022PA-45的Datasheet PDF文件第6页浏览型号CAT24C022PA-45的Datasheet PDF文件第7页浏览型号CAT24C022PA-45的Datasheet PDF文件第8页浏览型号CAT24C022PA-45的Datasheet PDF文件第10页浏览型号CAT24C022PA-45的Datasheet PDF文件第11页浏览型号CAT24C022PA-45的Datasheet PDF文件第12页 
CAT24CXX1/XX2  
Acknowledge Polling  
protected and becomes read only. The CAT24CXXX  
will accept both slave and byte addresses, but the  
memory location accessed is protected from  
programming by the device’s failure to send an  
acknowledge after the first byte of data is received.  
Disabling of the inputs can be used to take advantage of  
the typical write cycle time. Once the stop condition is  
issuedtoindicatetheendofthehost’swriteopration, the  
CAT24CXXXinitiatestheinternalwritecycle.ACKpolling  
can be initiated immediately. This involves issueing the  
start condition followed by the slave address for a write  
operation. If the CAT24CXXX is still busy with the write  
operation, no ACK will be returned. If a write operation  
hascompleted, anACKwillbereturnedandthehostcan  
then proceed with the next read or write operation.  
Read Operations  
The READ operation for the CAT24CXXX is initiated in  
the same manner as the write operation with one  
exception, that R/W bit is set to one. Three different  
READ operations are possible: Immediate/Current  
Address READ, Selective/Random READ and  
Sequential READ.  
WRITE PROTECTION  
The Write Protection feature allows the user to protect  
against inadvertent memory array programming. If the  
WP pin is tied to VCC, the entire memory array is  
Figure 9. Immediate Address Read Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
SDA LINE  
S
P
A
C
K
N
O
DATA  
A
C
K
SCL  
SDA  
8
9
8TH BIT  
DATA OUT  
NO ACK  
STOP  
24C1601 Fig. 8  
Doc No. 3000, Rev. A  
9

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