Datasheet > CAT24C022PA-45

CAT24C022PA-45

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
CATALYST		光电二极管
页数	文件大小	规格书
12页	71K
描述
Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

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CAT24C022PA-45 数据手册

CAT24CXX1/XX2

ACKNOWLEDGE

pointers of the CAT24CXXX. After receiving another

acknowledgefromtheSlave,theMasterdevicetransmits

thedatatobewrittenintotheaddressedmemorylocation.

The CAT24CXXX acknowledges once more and the

Master generates the STOP condition. At this time, the

device begins an internal programming cycle to non-

volatilememory.Whilethecycleisinprogress,thedevice

will not respond to any request from the Master device.

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data.

The CAT24CXXX responds with an acknowledge after

receivingaSTARTconditionanditsslaveaddress.Ifthe

device has been selected along with a write operation,

it responds with an acknowledge after receiving each 8-

bit byte.

Page Write

The CAT24CXXX writes up to 16 bytes of data in a single

write cycle, using the Page Write operation. The page

write operation is initiated in the same manner as the byte

write operation, however instead of terminating after the

initial byte is transmitted, the Master is allowed to send up

to 15 additional bytes. After each byte has been

transmitted, the CAT24CXXX will respond with an

acknowledge and internally increment the lower order

addressbitsbyone.Thehighorderbitsremainunchanged.

WhentheCAT24CXXXbeginsaREADmodeittransmits

8 bits of data, releases the SDA line and monitors the

line for an acknowledge. Once it receives this

acknowledge, the CAT24CXXX will continue to transmit

data.IfnoacknowledgeissentbytheMaster,thedevice

terminates data transmission and waits for a STOP

condition.

WRITE OPERATIONS

IftheMastertransmitsmorethan16bytesbeforesending

the STOP condition, the address counter ‘wraps around,’

and previously transmitted data will be overwritten.

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information

(with the R/W bit set to zero) to the Slave device. After

the Slave generates an acknowledge, the Master sends

a 8-bit address that is to be written into the address

When all 16 bytes are received, and the STOP condition

has been sent by the Master, the internal programming

cycle begins. At this point, all received data is written to

the CAT24CXXX in a single write cycle.

Figure 7. Byte Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS

DATA

SDA LINE

Figure 8. Page Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

DATA n

DATA n+1

DATA n+15

SDA LINE

Doc. No. 3000, Rev. A

1...5 6 789 10 11 12

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CAT24C022PA-45TE13	CATALYST	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog	获取价格
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CAT24C022PI-30	CATALYST	Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8	获取价格
CAT24C022PI-30TE13	CATALYST	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog	获取价格
CAT24C022PI-42	CATALYST	Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8	获取价格

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