Datasheet > CAT24C022PA-45

CAT24C022PA-45

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
CATALYST		光电二极管
页数	文件大小	规格书
12页	71K
描述
Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

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CAT24C022PA-45 数据手册

CAT24CXX1/XX2

Immediate/Current Address Read

and sends teh 8-bit byte requested. The master device

does not send an acknowledge but will generate a

STOP condition.

The CAT24CXXX’s address counter contains the

address of the last byte accessed, incremented by one.

In other words, if the last READ or WRITE access was

to address N, the READ immediately following would

accessdatafromaddressN+1. IfN=E(whereE=255for

the CAT24C021/022, E=511 for the CAT24C041/042,

E=1023 for the CAT24C081/082 and E=2047 for the

CAT24C161/162) then the counter will ‘wrap around’ to

address 0 and continue to clock out data. After the

CAT24CXX3 receives its slave address information

(with the R/W bit set to one), it issues an acknowledge,

then transmits the 8-bit byte requested. The master

device does not send an acknowledge, but will generate

a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by

eithertheImmediateAddressREADorSelectiveREAD

operations. After the CAT24CXXX sends the inital 8-bit

byte requested, the Master will responds with an

acknowledge which tells the device it requires more

data. The CAT24CXXX will continue to output an 8-bit

byte for each acknowledge, thus sending the STOP

condition.

The data being transmitted from the CAT24CXXX is

outputtedsequentiallywithdatafromaddressNfollowed

bydatafromaddressN+1.TheREADoperationaddress

counter increments all of the CAT24CXXX address bits

so that the entire memory array can be read during one

operation. If more than E (where E=255 for the

CAT24C021/022, E=511 for the CAT24C041/042,

E=1023 for the CAT24C081/082 and E=2047 for the

CAT24C161/162) bytes are read out, the counter will

‘wrap around’ and continue to clock out data bytes.

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a

READ operation. The Master device first performs a

‘dummy’writeoperationbysendingtheSTARTcondition,

slave address and byte addresses of the location it

wishes to read. After the CAT24CXXX acknowledges,

the Master device sends the START condition and the

slaveaddressagain,thistimewiththeR/Wbitsettoone.

The CAT24CXXX then responds with its acknowledge

Figure 10. Selective Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

SLAVE

ADDRESS

SDA LINE

DATA n

24C1601Fig.9

Figure 11. Sequential Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

24C1601Fig.10

Doc. No. 3000, Rev. A

1...7 8 91011 12

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与CAT24C022PA-45相关器件

型号	品牌	描述	获取价格	数据表
CAT24C022PA-45TE13	CATALYST	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog	获取价格
CAT24C022PI-25TE13	CATALYST	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog	获取价格
CAT24C022PI-28TE13	CATALYST	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog	获取价格
CAT24C022PI-30	CATALYST	Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8	获取价格
CAT24C022PI-30TE13	CATALYST	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog	获取价格
CAT24C022PI-42	CATALYST	Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8	获取价格

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