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CAT24AC128KE-REVA PDF预览

CAT24AC128KE-REVA

更新时间: 2024-10-28 15:29:11
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
11页 474K
描述
16KX8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.210 INCH, EIAJ, SOIC-8

CAT24AC128KE-REVA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.210 INCH, EIAJ, SOIC-8
针数:8Reach Compliance Code:unknown
风险等级:5.92最大时钟频率 (fCLK):0.4 MHz
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:5.3 mm内存密度:131072 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:16KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:2.03 mm
串行总线类型:I2C最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.25 mm最长写入周期时间 (tWC):5 ms
Base Number Matches:1

CAT24AC128KE-REVA 数据手册

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E
CAT24AC128  
128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins  
TM  
FEATURES  
I 1MHz (5V), 400kHz (2.5V) and 100kHz (1.8V) I2C  
I Commercial, industrial and extended  
bus comatibility  
automotive temperature ranges  
I 1.8 to 6 volt operation  
I Low power CMOS technology  
I Write protect feature  
– Entire array protected when WP at VIH  
I 1,000,000 program/erase cycles  
I 100 year data retention  
I Schmitt trigger filtered inputs for noise  
suppression  
I 64-Byte page write buffer  
I 8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or  
14-pin TSSOP  
I Self-timed write cycle with auto-clear  
DESCRIPTION  
The CAT24AC128 is a 128kbit Serial CMOS EEPROM  
internally organized as 16,384 words of 8 bits each.  
Catalyst’s advanced CMOS technology substantially  
reducesdevicepowerrequirements. TheCAT24AC128  
featuresa64-bytepagewritebuffer.Thedeviceoperates  
via the I2C bus serial interface and is available in 8-pin  
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three  
device address inputs allows up to 8 devices to share a  
common 2-wire I2C bus.  
BLOCK DIAGRAM  
PIN CONFIGURATION  
DIP Package (P, L)  
SOIC Package (J, K, W, X)  
EXTERNAL LOAD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
CC  
WP  
A0  
A1  
A2  
A0  
A1  
CC  
SENSE AMPS  
SHIFT REGISTERS  
D
OUT  
WP  
ACK  
A2  
SCL  
SDA  
SCL  
SDA  
V
V
CC  
SS  
V
V
SS  
SS  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
TSSOP Package (U14, Y14)  
512  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
A0  
V
WP  
NC  
NC  
NC  
CC  
START/STOP  
SDA  
A1  
NC  
NC  
NC  
A2  
LOGIC  
E2PROM  
256X512  
XDEC  
256  
SCL  
SDA  
V
8
SS  
CONTROL  
LOGIC  
WP  
PIN FUNCTIONS  
DATA IN STORAGE  
Pin Name  
Function  
SDA  
SCL  
WP  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
Write Protect  
SCL  
STATE COUNTERS  
VCC  
+1.8V to +6V Power Supply  
Ground  
SLAVE  
ADDRESS  
COMPARATORS  
A0  
A1  
A2  
VSS  
A0 - A2  
Device Address Inputs  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© 2004 by Catalyst Semiconductor, Inc.  
Doc. No. 1028, Rev. H  
1
Characteristics subject to change without notice  

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