Datasheet > CAT1021YI-30TE13

CAT1021YI-30TE13

更新时间： 2024-02-14 16:10:27

品牌	Logo	应用领域
安森美 - ONSEMI		光电二极管
页数	文件大小	规格书
20页	193K
描述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, LEAD AND HALOGEN FREE, TSSOP-8

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CAT1021YI-30TE13 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	TSSOP,	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.07
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.4 mm	湿度敏感等级：	1
信道数量：	1	功能数量：	1
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	3 mm
Base Number Matches：	1

CAT1021YI-30TE13 数据手册

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8TH B

ACK

CAT1021, CAT1022, CAT1023

EMBEDDED EEPROM OPERATON

The CAT1021/22/23 feature a 2−kbit embedded serial

EEPROM that supports the I C Bus data transmission

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

protocol. This Inter−Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter and

any device receiving data to be a receiver. The transfer is

controlled by the Master device which generates the serial

clock and all START and STOP conditions for bus access.

Both the Master device and Slave device can operate as

either transmitter or receiver, but the Master device controls

which mode is activated.

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition.

Start Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT1021/22/23 monitor the SDA

and SCL lines and will not respond until this condition is

met.

I²C Bus Protocol

The features of the I C bus protocol are defined as

Stop Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

follows:

1. Data transfer may be initiated only when the bus is

not busy.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master sends the address of the particular

slave device it is requesting. The four most significant bits

of the 8−bit slave address are programmable in metal and the

default is 1010.

The last bit of the slave address specifies whether a Read

or Write operation is to be performed. When this bit is set to

1, a Read operation is selected, and when set to 0, a Write

operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT1021/22/23 monitors the bus and

responds with an acknowledge (on the SDA line) when its

address matches the transmitted slave address. The

CAT1021/22/23 then perform a Read or Write operation

depending on the R/W bit.

HIGH

LOW

SCL

HD:DAT

SU:STA

HD:STA

SU:DAT

SU:STO

SDA IN

BUF

SDA OUT

Figure 3. Bus Timing

SCL

SDA

BYTE n

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 4. Write Cycle Timing

http://onsemi.com

1...6 7 8910 11 12...20

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与CAT1021YI-30TE13相关器件

型号	品牌	描述	获取价格	数据表
CAT1021YI42	ONSEMI	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, HALOGEN FREE AND ROHS COMPLIANT, MO-153, TSS	获取价格
CAT1021YI-42	CATALYST	Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer	获取价格
CAT1021YI-42	ONSEMI	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, HALOGEN FREE AND ROHS COMPLIANT, MO-153, TSS	获取价格
CAT1021YI-42-GT2	CATALYST	Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer	获取价格
CAT1021YI-42-GT3	ONSEMI	Supervisory Circuits with I2C Serial 2k-bit CMOS	获取价格
CAT1021YI-42-GT3	CATALYST	Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer	获取价格

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