Datasheet > CA3224

CA3224

更新时间： 2024-02-05 18:55:50

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
6页	65K
描述
Automatic Picture Tube Bias Control Circuit

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中文翻译

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技术参数
数据手册

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CA3224 技术参数

生命周期：	Contact Manufacturer	零件包装代码：	DIP
包装说明：	DIP,	针数：	22
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.69	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDIP-T22	长度：	27.75 mm
功能数量：	1	端子数量：	22
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
认证状态：	Not Qualified	座面最大高度：	5.33 mm
最大供电电压 (Vsup)：	11 V	最小供电电压 (Vsup)：	9 V
表面贴装：	NO	温度等级：	INDUSTRIAL
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	10.16 mm
Base Number Matches：	1

CA3224 数据手册

CA3224E

Automatic Picture Tube Bias Control Circuit

November 1996

Features

Description

• Automatic Picture Tube Bias Cutoff Control

• Automatic Background Color Balance

• Eliminates Grey Scale Adjustments

• Compensates for Cathode-to-Heater Leakage

• Electrostatic Protection on All Pins

• Servo Loop Design

The CA3224E is an automatic picture tube bias control cir-

cuit used in color TV receiver CRT drive circuits. It is used to

provide dynamic bias control of the grey scale both initially

and over the CRT operating life, compensating for CRT cut-

off changes.

The CA3224E provides automatic continuous control of the

cutoff current in each gun of a three-gun color CRT. From an

input pulse amplitude proportional to the difference between

the desired and the actual CRT cutoff, a gated sample/hold

circuit generates a DC correction voltage which correctly

biases the CRT driver circuit. The sample/hold bias correc-

tion takes place each frame following the vertical blanking.

Figure 1 shows a block diagram of the CA3224E. The func-

tions include three identical servo loop transconductance

• Wide Dynamic Range

• Three-Gun Control

• Minimal External Components

Ordering Information

ampliﬁers with a sample/hold switch and buffer ampliﬁer plus

control logic, internal bias and a mode switch.

TEMP.

PKG.

NO.

PART NUMBER RANGE ( C)

PACKAGE

22 Ld PDIP

CA3224E

-40 to 85

E22.4

Pinout

CA3224E

(PDIP)

TOP VIEW

GROUND

CHANNEL 1 INPUT

CHANNEL 1 HOLD CAP

CHANNEL 1 OUTPUT

CHANNEL 2 HOLD CAP

CHANNEL 2 OUTPUT

CHANNEL 3 HOLD CAP

CHANNEL 3 OUTPUT

CHANNEL 1 FREQ COMPENSATION

CHANNEL 2 INPUT

CHANNEL 2 FREQ COMPENSATION

CHANNEL 3 INPUT

CHANNEL 3 FREQ COMPENSATION

VERTICAL INPUT

BYPASS

REF

AUTO BIAS LEVEL ADJUST

GROUND

HORIZONTAL INPUT

AUTO BIAS PULSE OUTPUT

PROGRAM PULSE OUTPUT

GRID PULSE OUTPUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 1553.1

8-56

12 3 4 5 6

中文翻译

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与CA3224相关器件

型号	品牌	获取价格	描述	数据表
CA3224E	INTERSIL	获取价格	Automatic Picture Tube Bias Control Circuit
CA3224E_02	INTERSIL	获取价格	Automatic Picture Tube Bias Control Circuit
CA3227	INTERSIL	获取价格	High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz
CA3227_02	INTERSIL	获取价格	High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz
CA3227E	INTERSIL	获取价格	High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz
CA3227M	INTERSIL	获取价格	High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz
CA3227M96	INTERSIL	获取价格	High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz
CA3228	INTERSIL	获取价格	Speed Control System with Memory
CA3228	HARRIS	获取价格	Speed Control System with Memory
CA3228E	HARRIS	获取价格	Speed Control System with Memory

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