Datasheet > C9850AT

C9850AT

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
19页	220K
描述
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, TSSOP-56

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C9850AT 数据手册

ADVANCED INFORMATION

C9850

High Performance Pentium III Clock Generator

Vdd

Strapping Resistor Options for pins with internal

Pull-ups:

Rup

The power up bidirectional pins have a large value pull-

up each (250KΩ), therefore, a selection “1” is the

default. If the system uses a slow power supply (over

3mS settling time), then it is recommended to use an

external Pullup (Rup) in order to insure a high

50K

IMI C9850

Load

Bidirectional

JP1

JUMPER

selection. In this case, the designer may choose one of

two configurations, see Fig. 2A and Fig. 2B.

Fig.2A

Fig. 2A represents an additional pull up resistor 50KΩ

connected from the pin to the power line, which allows

a faster pull to a high level.

Rdn

If a selection “0” is desired, then a jumper is placed on

JP1 to a 5KΩ resistor as implemented as shown in

Fig.2A. Please note the selection resistors (Rup, and

Rdn) are placed before the Damping resistor (Rd)

close to the pin.

JP2

Vdd

3 Way Jumper

Fig. 2B represent a single resistor 10KΩ connected to a

3 way jumper, JP2. When a “1” selection is desired, a

jumper is placed between leads1 and 3. When a “0”

selection is desired, a jumper is placed between leads

1 and 2.

Rsel

10K

IMI C9850

Load

Bidirectional

Fig.2B

Maximum Ratings¹

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

field; however, precautions should be taken to avoid

application of any voltage higher than the maximum

rated voltages to this circuit. For proper operation, Vin

and Vout should be constrained to the range:

VSS<(Vin or Vout)<VDD

Maximum Input Voltage:

Storage Temperature:

Operating Temperature:

Maximum ESD protection

Maximum Power Supply:

VSS - 0.5V

VDD + 0.7V

-65°C to + 150°C

0°C to +85°C

2000V

Unused inputs must always be tied to an appropriate

logic voltage level (either VSS or VDD)

5.5V

¹Note: 1. The voltage on any input or I/O cannot exceed the

power pin during power-up. Power supply sequencing is

NOT required.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07067 Rev. *A

12/22/2002

Page 4 of 19

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