Datasheet > C9850AT

C9850AT

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
19页	220K
描述
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, TSSOP-56

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C9850AT 数据手册

ADVANCED INFORMATION

C9850

High Performance Pentium III Clock Generator

AC Parameters (Cont.)

133 MHz CPU

100 MHz CPU

Characteristic

Symbol

TPeriod

Units

Notes

2, 9

Min

15.0

5.25

5.05

0.5

Max

16.0

N/A

2.0

Min

15.0

5.25

5.05

0.5

Max

15.2

N/A

2.0

3V66 CLK period

3V66 CLK high time

3V66 CLK low time

3V66 CLK rise time

3V66 CLK fall time

3V66 Duty Cycle

THIGH

TLOW

TRISE

TFALL

Tdc

5, 10

6, 10

0.5

2.0

0.5

2.0

3V66 to 3V66 clock skew

3V66 Cycle to Cycle jitter

PCI CLK period

PCI CLK high time

PCI CLK low time

PCI CLK rise time

PCI CLK fall time

PCI Duty Cycle

Tskew

TJcc

250

300 pS

250

300 pS

2, 9

5, 10

6, 10

TPeriod

THIGH

TLOW

TRISE

TFALL

Tdc

30.0

12.0

0.5

30.0

12.0

0.5

2.0

PCI to PCI clock skew

PCI Cycle to Cycle jitter

Output enable delay (all outputs)

Output disable delay (all outputs)

Tskew

TJcc

500

10.0

500

10.0

tpZL, tpZH

tpLZ, tpZH

Tstable

1.0

All clock Stabilization from power-up

Notes:

1. All output drivers have monotonic rise/fall times through the specified VOL/VOH levels.

2. Period, jitter, offset and skew measured on rising edge @ 1.25V for 2.5V clocks and @1.5V for 3.3V clocks.

3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the host clock divided by three at

Host = 100 MHz.

4. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided

by three for Host = 100 MHz.

5. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.

6. TLOW is measured at 0.4V for all outputs.

7. The time specified is measured from when VDD achieves its nominal operating level (typical condition VDD = 3.3V)

till the frequency output is stable and operating within specification.

8. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V

9. The average period over any 1 uS period of time is greater than the minimum specified period.

10. Calculated at minimum edge-rate (1V/nS) to guarantee 45/55% duty-cycle.

11. CPU clock test load is Rs=33.2 Ohms, Rp = 49.9.

12. 20% and 80%

13. Measured at 1.25 Volts

14. Measured at 1.50 Volts

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07067 Rev. *A

12/22/2002

Page 7 of 19

1...4 5 678 9 10...19

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