Datasheet > C9850AT

C9850AT

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
19页	220K
描述
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, TSSOP-56

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C9850AT 数据手册

ADVANCED INFORMATION

C9850

High Performance Pentium III Clock Generator

Pin Description (cont.)

PIN No.

Pin Name

VDDU

VSSU

I/O Description

Power pin recommended for 48 MHz dedicated use.

Ground pin recommended for 48 MHz dedicated use.

Power pins recommended for PCI dedicated use.

Ground pins recommended for PCI dedicated use.

Power pin recommended for Ref clock and Xtal dedicated use.

22, 16, 10

19, 13, 7

VDDP

VSSP

VDDR

VSSR

Ground pin recommended for Ref clock and Xtal dedicated use.

Note: All pin numbers that are followed with an astirik (*) contain internal pull-up resistors. These internal devices are

sufficient enough to guarantee a logic 1 will be sensed internally of no external circuitry is connected.

Power on Bi-Directional Pins

Power Up Condition:

Pins 2, 3, 25, and 26 are Power up bi-directional pins and are used for different features in this device (see Pin

description, Page 2). During power-up, these pins are in input mode (see Fig 2, below), therefore, they are considered

input select pins internal to the IC. After a settling time, the Selection data is latch into internal control registers and

these pins become toggling clock outputs.

VDD Rail

Power Supply

Ramp

Ref1/MultSel0

Ref2/MultSel1

Hi-Z Inputs

Toggle Outputs

48M0/SelA

48M1/SelB

Select Data is latched into register then pin becomes clock output signal.

Fig. 1

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07067 Rev. *A

12/22/2002

Page 3 of 19

1 234 5 6 7...19

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