C8051F061
25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
Two 16-Bit ADCs
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
-
-
-
-
±0.75 LSB INL; guaranteed no missing codes
Programmable throughput up to 1 Msps (each ADC)
Configurable as two single-ended or one differential ADC
DMA to XRAM or external memory interface
-
-
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
Memory
-
-
-
4352 bytes data RAM
Data-dependent windowed interrupt generator
64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
10-Bit ADC
are reserved)
-
-
-
Programmable throughput up to 200 ksps
External parallel data memory interface
8 external inputs
Built-in temperature sensor (±3 °C)
CAN Bus 2.0B
-
-
32 message objects
”Mailbox" implementation only interrupts CPU when needed
Two 12-Bit DACs
-
Can synchronize outputs to timers for jitter-free waveform generation
Digital Peripherals
Three Comparators
Internal Voltage Reference
-
-
24 port I/O; all are 5 V tolerant
Precision V Monitor/Brown-out Detector
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
DD
ports available concurrently
On-Chip JTAG Debug & Boundary Scan
-
-
-
-
Programmable 16-bit counter array with 6 capture/compare modules
-
-
-
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timers or PCA
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
Clock Sources
pods, and sockets
-
-
Internal programmable 2% oscillator: up to 24.5 MHz
External oscillator: Crystal, RC, C, or Clock
-
IEEE1149.1 compliant boundary scan
Supply Voltage: 2.7 to 3.6 V
64-Pin TQFP
-
-
Typical operating current: 10 mA at 25 MHz
Multiple power saving sleep and shutdown modes
- Temperature Range: –40 to +85 °C
VDD
VDD
P0.0
P0.7
Digital Power
VDD
P0
UART0
UART1
SMBus
SPI Bus
PCA
DGND
DGND
DGND
Drv
8
0
5
1
C
R
O
S
S
B
A
R
AV+
Analog Power
AGND
P1.0/AIN2.0
P1.7/AIN2.7
P1
TCK
Drv
Boundary Scan
Debug HW
JTAG
Logic
TMS
TDI
TDO
P2.0
P2.7
P2
Timers 0,
1, 2,3,4
Reset
/RST
Drv
SFR Bus
MONEN
VDD Monitor
WDT
P0, P1,
P2, P3
Latches
External
Oscillator
Circuit
XTAL1
XTAL2
P3
Drv
System Clock
C
o
r
64 kB
25 MHz 2%
Internal
FLASH
CAN 2.0B
CTX
CRX
Oscillator
(32 Message Objects)
VREF
VREF
256 byte
RAM
VREF2
VREF2
Temp
A
M
U
X
ADC
Sensor
DAC0
8:1
DAC0
DAC1
200 ksps
(10-Bit)
(12-Bit)
4 kB
e
AVDD
RAM
ADGND
P2.6
P2.7
CP0
+
-
AV+
AGND
P2.2
P2.3
CP1
VREF0
+
VRGND0
-
P2.4
P2.5
CP2
+
-
ADC0
1 Msps
(16-Bit)
AIN0
R
E
S
U
L
T
0
AIN0G
External Data
Memory Bus
P4 Latch
VBGAP0
P4
CNVSTR0
DRV
Ctrl Latch
AVDD
ADGND
P5 Latch
Addr15-8
P6 Latch
P5
AV+
AGND
EMIF
Cntrl
DRV
+
Σ
-
VREF1
D
I
VRGND1
DMA
P6
F
F
R
E
S
U
L
T
1
DRV
ADC1
Addr7-0
P7 Latch
AIN1
1Msps
AIN1G
(16-Bit)
P7
DRV
Data Latch
VBGAP1
CNVSTR1
CAN 2.0B
Copyright © 2004 by Silicon Laboratories
6.15.2004