C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Mixed Signal ISP Flash MCU Family
Analog Peripherals
High Speed 8051 µC Core
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10 or 12-bit SAR ADC
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Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
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± 1 LSB INL
Programmable throughput up to 100 ksps
Up to 8 external inputs; programmable as single-
ended or differential
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100 MIPS or 50 MIPS throughput with on-chip PLL
2-cycle 16 x 16 MAC engine (C8051F120/1/2/3 and
C8051F130/1/2/3 only)
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Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor
Memory
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8-bit SAR ADC (‘F12x Only)
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8448 bytes internal data RAM (8 k + 256)
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Programmable throughput up to 500 ksps
8 external inputs (single-ended or differential)
Programmable amplifier gain: 4, 2, 1, 0.5
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128 or 64 kB Banked Flash; in-system programma-
ble in 1024-byte sectors
Two 12-bit DACs (‘F12x Only)
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External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
•
Can synchronize outputs to timers for jitter-free wave-
form generation
Digital Peripherals
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Two Analog Comparators
Voltage Reference
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8 byte-wide port I/O (100TQFP); 5 V tolerant
4 Byte-wide port I/O (64TQFP); 5 V tolerant
Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
Programmable 16-bit counter/timer array with
6 capture/compare modules
V
Monitor/Brown-Out Detector
DD
On-Chip JTAG Debug & Boundary Scan
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On-chip debug circuitry facilitates full-speed, non-
intrusive in-circuit/in-system debugging
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
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5 general purpose 16-bit counter/timers
Dedicated watchdog timer; bi-directional reset pin
Clock Sources
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IEEE1149.1 compliant boundary scan
Complete development kit
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Internal precision oscillator: 24.5 MHz
Flexible PLL technology
External Oscillator: Crystal, RC, C, or clock
100-Pin TQFP or 64-Pin TQFP Packaging
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Temperature Range: –40 to +85 °C
Voltage Supples
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RoHS Available
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Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)
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Power saving sleep and shutdown modes
ANALOG PERIPHERALS
DIGITAL I/O
UART0
VREF
Port 0
10/12-bit
100ksps
ADC
UART1
Port 1
SMBus
PGA
Port 2
SPI Bus
PCA
+
-
+
Port 3
TEMP
SENSOR
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Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
VOLTAGE
COMPARATORS
Port 4
Port 5
Port 6
12-Bit
DAC
8-bit
PGA
500ksps
ADC
12-Bit
DAC
Port 7
C8051F12x Only
64 pin 100 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
128/64 kB 8448 B
16 x 16 MAC
(50 or 100MIPS) ISP FLASH SRAM ('F120/1/2/3, 'F13x)
20
DEBUG
CIRCUITRY
CLOCK / PLL
CIRCUIT
JTAG
INTERRUPTS
Preliminary Rev. 1.4 12/05
Copyright © 2005 by Silicon Laboratories
C8051F12x C8051F13x