C8051F065
25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
Two 16-Bit ADCs
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Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
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-
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±0.75 LSB INL; no missing codes
Programmable throughput up to 1 Msps (each ADC)
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Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
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1 external input each; programmable as two single-ended or one differ-
ential ADC
Memory
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-
DMA to XRAM or external memory interface
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-
4352 bytes data RAM
Data-dependent windowed interrupt generator
64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
Three Comparators
are reserved)
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16 programmable hysteresis values
Configurable to generate interrupts or reset
Digital Peripherals
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-
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24 port I/O; all are 5 V tolerant
Internal Voltage Reference
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
Precision V Monitor/Brown-out Detector
DD
ports available concurrently
On-Chip JTAG Debug & Boundary Scan
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-
-
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Programmable 16-bit counter/timer array with six capture/compare mod-
ules
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On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timers or PCA
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
Clock Sources
pods, and sockets
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Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
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IEEE1149.1 compliant boundary scan
Supply Voltage: 2.7 to 3.6 V
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Typical operating current: 18 mA at 25 MHz
Multiple power saving sleep and shutdown modes
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64-Pin TQFP
Temperature Range: –40 to +85 °C
VDD
VDD
P0.0
P0.7
Digital Power
VDD
P0
UART0
DGND
Drv
DGND
8
0
5
1
DGND
UART1
C
AV+
Analog Power
AGND
R
SMBus
P1.0/AIN2.0
P1.7/AIN2.7
P1
O
TCK
TMS
TDI
Drv
SPI Bus
PCA
Boundary Scan
Debug HW
JTAG
Logic
S
S
B
A
R
TDO
P2.0
P2.7
P2
Timers 0,
1, 2,3,4
Reset
RST
Drv
SFR Bus
MONEN
VDD Monitor
WDT
P0, P1,
P2, P3
Latches
External
Oscillator
Circuit
XTAL1
XTAL2
P3
Drv
System Clock
C
o
r
64 kB
25 MHz 2%
Internal
Oscillator
FLASH
VREF
VREF
256 Byte
RAM
P2.6
P2.7
CP0
+
-
P2.2
P2.3
P2.4
P2.5
CP1
4 kB
+
-
e
AVDD
RAM
ADGND
CP2
+
-
AV+
AGND
VREF0
VRGND0
ADC0
1 Msps
(16-Bit)
AIN0
R
E
S
U
L
T
0
AIN0G
External Data
Memory Bus
P4 Latch
VBGAP0
P4
CNVSTR0
DRV
Ctrl Latch
AVDD
ADGND
P5 Latch
Addr15-8
P6 Latch
P5
AV+
AGND
EMIF
Cntrl
DRV
+
Σ
-
D
I
VREF1
VRGND1
DMA
P6
DRV
F
F
R
E
S
U
L
T
1
ADC1
1 Msps
(16-Bit)
Addr7-0
P7 Latch
AIN1
AIN1G
P7
DRV
Data Latch
VBGAP1
CNVSTR1
Precision Mixed Signal
Copyright © 2004 by Silicon Laboratories
7.28.04