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C8051F066 PDF预览

C8051F066

更新时间: 2024-02-16 18:45:33
品牌 Logo 应用领域
芯科 - SILICON 闪存
页数 文件大小 规格书
2页 192K
描述
25 MIPS, 32 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU

C8051F066 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:QFP
包装说明:TFQFP, TQFP100,.63SQ针数:100
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:8.1具有ADC:YES
地址总线宽度:16位大小:8
CPU系列:8051最大时钟频率:25 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:8JESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
湿度敏感等级:3I/O 线路数量:59
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装等效代码:TQFP100,.63SQ封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3 V认证状态:Not Qualified
RAM(字节):4352ROM(单词):32768
ROM可编程性:FLASH座面最大高度:1.2 mm
速度:25 MHz子类别:Microcontrollers
最大供电电压:3.6 V最小供电电压:2.7 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

C8051F066 数据手册

 浏览型号C8051F066的Datasheet PDF文件第2页 
C8051F066  
25 MIPS, 32 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU  
Analog Peripherals  
High-Speed 8051 µC Core  
Two 16-Bit ADCs  
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2  
system clocks  
-
-
-
±0.75 LSB INL; no missing codes  
Programmable throughput up to 1 Msps (each ADC)  
-
Up to 25 MIPS throughput with 25 MHz system clock  
Expanded interrupt handler  
-
1 external input each; programmable as two single-ended or one differ-  
ential ADC  
Memory  
-
-
DMA to XRAM or external memory interface  
-
-
4352 bytes data RAM  
Data-dependent windowed interrupt generator  
32 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes  
Three Comparators  
are reserved)  
-
16 programmable hysteresis values  
Configurable to generate interrupts or reset  
-
External parallel data memory interface  
-
Digital Peripherals  
Internal Voltage Reference  
-
-
59 port I/O; all are 5 V tolerant  
Precision V Monitor/Brown-out Detector  
DD  
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial  
On-Chip JTAG Debug & Boundary Scan  
ports available concurrently  
-
Programmable 16-bit counter/timer array with six capture/compare mod-  
ules  
-
-
-
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system  
debug (no emulator required)  
-
-
-
5 general-purpose 16-bit counter/timers  
Dedicated watchdog timer; bidirectional reset  
Real-time clock mode using timers or PCA  
Provides breakpoints, single stepping, watchpoints, stack monitor  
Inspect/modify memory and registers  
Superior performance to emulation systems using ICE-chips, target  
pods, and sockets  
Clock Sources  
-
IEEE1149.1 compliant boundary scan  
-
-
-
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation  
External oscillator: Crystal, RC, C, or Clock  
Can switch between clock sources on-the-fly  
Supply Voltage: 2.7 to 3.6 V  
-
Typical operating current: 18 mA at 25 MHz  
Multiple power saving sleep and shutdown modes  
-
100-Pin TQFP  
Temperature Range: –40 to +85 °C  
VDD  
VDD  
P0.0  
P0.7  
Digital Power  
VDD  
P0  
UART0  
DGND  
Drv  
DGND  
8
0
5
1
DGND  
UART1  
C
AV+  
Analog Power  
AGND  
R
SMBus  
P1.0/AIN2.0  
P1.7/AIN2.7  
P1  
O
TCK  
TMS  
TDI  
Drv  
SPI Bus  
PCA  
Boundary Scan  
Debug HW  
JTAG  
Logic  
S
S
B
A
R
TDO  
P2.0  
P2.7  
P2  
Timers 0,  
1, 2,3,4  
Reset  
/RST  
Drv  
SFR Bus  
MONEN  
VDD Monitor  
WDT  
P0, P1,  
P2, P3  
Latches  
External  
Oscillator  
Circuit  
P3.0  
P3.7  
XTAL1  
XTAL2  
P3  
Drv  
System Clock  
C
o
r
32 kB  
25 MHz 2%  
Internal  
Oscillator  
FLASH  
VREF  
VREF  
256 Byte  
RAM  
P2.6  
P2.7  
P2.2  
P2.3  
P2.4  
P2.5  
CP0  
+
-
CP1  
4 kB  
+
-
e
AVDD  
RAM  
ADGND  
CP2  
+
-
AV+  
AGND  
VREF0  
VRGND0  
ADC0  
1 Msps  
(16-Bit)  
AIN0  
R
E
S
U
L
T
0
AIN0G  
External Data  
Memory Bus  
P4 Latch  
VBGAP0  
CNVSTR0  
P4.5  
P4.6  
P4.7  
P4  
Bus Control  
DRV  
Ctrl Latch  
AVDD  
ADGND  
P5.0  
P5 Latch  
Addr15-8  
P6 Latch  
P5  
AV+  
Address Bus  
AGND  
EMIF  
Cntrl  
DRV  
P5.7  
P6.0  
+
Σ
-
D
I
VREF1  
VRGND1  
DMA  
P6  
DRV  
F
F
R
E
S
U
L
T
1
ADC1  
1 Msps  
(16-Bit)  
Addr7-0  
P7 Latch  
P6.7  
P7.0  
P7.7  
AIN1  
AIN1G  
P7  
Data Bus  
DRV  
Data Latch  
VBGAP1  
CNVSTR1  
Precision Mixed Signal  
Copyright © 2004 by Silicon Laboratories  
7.28.04  

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