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C8051F046 PDF预览

C8051F046

更新时间： 2024-01-08 01:17:49
品牌 Logo 应用领域
芯科 - SILICON 闪存微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
2页 413K
描述
25 MIPS, 32 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU

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中文翻译

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C8051F046 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.74具有ADC：YES
地址总线宽度：16位大小：8
最大时钟频率：25 MHzDAC 通道：NO
DMA 通道：NO外部数据总线宽度：8
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
长度：14 mmI/O 线路数量：64
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °CPWM 通道：YES
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
ROM（单词）：32768ROM可编程性：FLASH
座面最大高度：1.2 mm速度：25 MHz
最大供电电压：3.6 V最小供电电压：2.7 V
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

C8051F046 数据手册

 浏览型号C8051F046的Datasheet PDF文件第2页 
C8051F046  
25 MIPS, 32 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU  
Analog Peripherals  
Memory  
10-Bit ADC  
-
-
4352 bytes data RAM  
-
-
-
-
-
-
±1 LSB INL; guaranteed monotonic  
32 kB Flash; in-system programmable in 512-byte sectors (512 bytes  
are reserved)  
Programmable throughput up to 100 ksps  
13 external inputs; programmable as single-ended or differential  
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5  
Data-dependent windowed interrupt generator  
Built-in temperature sensor (±3 °C)  
-
External parallel data memory interface  
CAN Bus 2.0B  
-
-
32 message objects  
”Mailbox" implementation only interrupts CPU when needed  
High-Voltage Differential Amplifier  
Digital Peripherals  
-
-
-
60 V common mode input range  
Offset adjust from –60 to +60 V  
16 gain settings from 0.05 to 16  
-
-
64 port I/O; all are 5 V tolerant  
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial  
ports available concurrently  
Programmable 16-bit counter array with 6 capture/compare modules  
-
-
-
-
Three Comparators  
5 general-purpose 16-bit counter/timers  
Dedicated watchdog timer; bidirectional reset  
Real-time clock mode using timer 3 or PCA  
Internal Voltage Reference  
Precision V Monitor/Brown-out Detector  
DD  
On-Chip JTAG Debug & Boundary Scan  
Clock Sources  
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system  
debug (no emulator required)  
Provides breakpoints, single stepping, watchpoints, stack monitor, pro-  
gram trace memory  
-
-
Internal programmable 2% oscillator: up to 25 MHz  
-
External oscillator: Crystal, RC, C, or Clock  
Supply Voltage: 2.7 to 3.6 V  
-
-
Inspect/modify memory and registers  
-
-
Typical operating current: 10 mA at 25 MHz  
Superior performance to emulation systems using ICE-chips, target  
pods, and sockets  
IEEE1149.1 compliant boundary scan  
Multiple power saving sleep and shutdown mode  
-
100-Pin TQFP  
High-Speed 8051 µC Core  
Temperature Range: –40 to +85 °C  
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2  
system clocks  
-
-
Up to 25 MIPS throughput with 25 MHz system clock  
Expanded interrupt handler  
VDD  
VDD  
Digital Power  
UART0  
P0.0  
P0.7  
P0  
Drv  
VDD  
DGND  
DGND  
DGND  
AV+  
AV+  
AV+  
AGND  
AGND  
AGND  
UART1  
8
C
R
O
S
S
B
A
R
SMBus  
SPI Bus  
PCA  
SFR Bus  
P1.0  
P1.7  
Analog Power  
0
5
1
P1  
Drv  
Timers  
0,1,2,3,4  
P2.0/CPx  
P2.7/CPx  
TCK  
TMS  
TDI  
P2  
Drv  
Boundary Scan  
Debug HW  
JTAG  
Logic  
Port  
0,1,2,3  
&4  
TDO  
32 kB  
FLASH  
Reset  
RST  
P3.0/AINAMUX0  
P3.7/AINAMUX7  
P3  
Drv  
Latches  
VDD  
Monitor  
WDT  
MONEN  
C
o
r
32x136  
CANRAM  
CANTX  
CANRX  
CAN  
2.0B  
External  
Oscillator  
Circuit  
XTAL1  
XTAL2  
System  
Clock  
256 byte  
RAM  
VREF  
VREF  
4 kB  
XRAM  
e
P2.0  
P2.1  
Internal  
2%  
Oscillator  
+
-
CP0  
P2.2  
P2.3  
+
-
CP1  
P2.4  
P2.5  
+
-
CP2  
VREF0  
AIN0.0  
AIN0.1  
AIN0.2  
AIN0.3  
P4.0  
A
M
U
X
ADC  
100 ksps  
(10-Bit)  
P4  
DRV  
P4.4  
Port 4 <from crossbar>  
Bus Control  
Prog  
Gain  
P4.5/ALE  
P4.6/RD  
P4.7/WR  
External Data Memory Bus  
Ctrl Latch  
P5.0/A0  
P5 Latch  
Addr [7:0]  
P6 Latch  
Addr [15:8]  
P5  
DRV  
Address [15:0]  
TEMP  
SENSOR  
P5.7/A7  
P6.0/A8  
A
P6  
DRV  
M
U
X
8:2  
P6.7/A15  
P7.0/D0  
P7 Latch  
P7  
DRV  
HVAIN+  
HVAIN-  
Data [7:0]  
HVAMP  
P7.7/D7  
Data Latch  
HVREF  
HVCAP  
CAN 2.0B  
Copyright © 2004 by Silicon Laboratories  
10.11.2004  
12

中文翻译

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