Datasheet > C1608C0G1E682J

C1608C0G1E682J

更新时间： 2024-11-06 09:44:47

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Evaluation Board provides the design engineer with a fully functional

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C1608C0G1E682J 数据手册

National Semiconductor

Application Note 2066

Eric Lee

LM25119 Evaluation Board

September 28, 2010

ed to the J6 (OUT2+) and J5 (OUT2-/GND). Be sure to

choose the correct connector and wire size when attaching

the source power supply and the load.

Introduction

The LM25119EVAL evaluation board provides the design en-

gineer with a fully functional dual output buck converter, em-

ploying the LM25119 Dual Emulated Current Mode Syn-

chronous Buck Controller. The evaluation board is designed

to provide both 3.3V and 1.8V outputs over an input range of

6.0V to 36V. Also the evaluation board can be easily config-

ured for a single 3.3V, 16A regulator.

SOURCE POWER

The power supply and cabling must present low impedance

to the evaluation board. Insufficient cabling or a high

impedance power supply will droop during power supply ap-

plication with the evaluation board inrush current. If large

enough, this droop will cause a chattering condition during

power up. During power down, insufficient cabling or a high

impedance power supply will overshoot. This overshoot will

cause a non-monotonic decay on the output.

Performance of the Evaluation

Board

•

Input Voltage Range: 6.0V to 36V

Output Voltage: 3.3V (CH1), 1.8V (CH2)

Output Current: 8A (CH1), 8A (CH2)

Nominal Switching Frequency: 230 KHz

Synchronous Buck Operation: Yes

Diode Emulation Mode: Yes

An additional external bulk input capacitor may be required

unless the output voltage droop/overshoot of the source pow-

er is less than 0.5V. In this board design, UVLO setting is

conservative while UVLO hysteresis setting is aggressive.

Minimum input voltage can goes down with an aggressive

design. Minimum operating input voltage depends on the out-

put voltage droop/overshoot of the source power supply and

the forced off-time of the LM25119. Refer to the LM25119

datasheet for complete design information.

Hiccup Mode Overload Protection: Yes

External VCC Sourcing: No

Powering and Loading

Consideration

When applying power to the LM25119 evaluation board, cer-

tain precautions need to be followed. A misconnection can

damage the assembly.

When using an electronic load, it is strongly recommended to

power up the evaluation board at light load and then slowly

increase the load. If it is desired to power up the evaluation

board at maximum load, resistor banks must be used. In gen-

eral, electronic loads are best suited for monitoring steady

state waveforms.

PROPER BOARD CONNECTION

AIR FLOW

The input connections are made to the J1 (VIN) and J2 (RTN/

GND) connectors. The CH1 load is connected to the J3

(OUT1+) and J4 (OUT1-/GND) and the CH2 load is connect-

Prolonged operation with high input voltage at full power will

cause the MOSFETs to overheat. A fan with a minimum of

200LFM should be always provided.

30126101

FIGURE 1. Typical Evaluation Setup

301261

www.national.com

12 3 4 5 6 7...10

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与C1608C0G1E682J相关器件

型号	品牌	获取价格	描述	数据表
C1608C0G1E682J080AA	TDK	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 25V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.0068uF
C1608C0G1E682J080AA_17	TDK	获取价格	Multilayer Ceramic Chip Capacitors
C1608C0G1E682JT	TDK	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 25V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.0068uF
C1608C0G1E822J080AA	TDK	获取价格	CAP CER 8200PF 25V C0G 0603
C1608C0G1E822J080AA_17	TDK	获取价格	Multilayer Ceramic Chip Capacitors
C1608C0G1H010B	TDK	获取价格	CAP CER 1PF 50V C0G 0603
C1608C0G1H010B050A	TDK	获取价格	Multilayer Ceramic Chip Capacitors
C1608C0G1H010BT	TDK	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 50V, 10% +Tol, 10% -Tol, C0G, 30ppm/Cel TC, 0.0000
C1608C0G1H010BTXXXX	TDK	获取价格	General Application
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