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BU9882FV-WE2 PDF预览

BU9882FV-WE2

更新时间： 2024-02-20 23:00:04
品牌 Logo 应用领域
罗姆 - ROHM 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
23页 647K
描述
EDID Memory (For display)

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BU9882FV-WE2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：ROHS COMPLIANT, SSOP-14针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：1.45
Is Samacsys：N最大时钟频率 (fCLK)：0.4 MHz
JESD-30 代码：R-PDSO-G14长度：5 mm
内存密度：2048 bit内存集成电路类型：EEPROM
内存宽度：8功能数量：1
端口数量：2端子数量：14
字数：256 words字数代码：256
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256X8
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH并行/串行：SERIAL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3/5 V
认证状态：Not Qualified座面最大高度：1.25 mm
串行总线类型：I2C最大待机电流：0.000005 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：4 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm最长写入周期时间 (tWC)：10 ms
Base Number Matches：1

BU9882FV-WE2 数据手册

 浏览型号BU9882FV-WE2的Datasheet PDF文件第4页浏览型号BU9882FV-WE2的Datasheet PDF文件第5页浏览型号BU9882FV-WE2的Datasheet PDF文件第6页浏览型号BU9882FV-WE2的Datasheet PDF文件第8页浏览型号BU9882FV-WE2的Datasheet PDF文件第9页浏览型号BU9882FV-WE2的Datasheet PDF文件第10页 
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,  
BU9882-W,BU9882F-W,BU9882FV-W  
Technical Note  
○Random Read  
The Random read operation allows the Master to access any memory location. This operation involves a two-step  
process. First, the Master issues a Write command that includes the START condition and the Slave address field  
(with R/W set to “0”) followed by the word address of the word to be read. This procedure sets the internal address  
counter of the BR24C21/F/FJ/FV to the desired address. After the word address Acknowledge is received by the  
Master, the Master immediately re-issues a START condition followed by the Slave address field with R/W set to “1.”  
The device will respond with an Acknowledge and then transmit the 8-data bits stored at the addressed location. If the  
Master does not acknowledge the transmission but does generate the STOP condition, the IC will discontinue  
transmission.  
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE  
ADDRESS  
WORD  
ADDRESS（ｎ）  
SLAVE  
ADDRESS  
DATA(n)  
SDA  
LINE  
WA  
0
WA  
6
1
0
1
0
*
*
*
*
1
0
1
0
*
*
*
D7  
D0  
A
C
K
R
/
W K  
A
C
A
C
K
R
/
W K  
A
C
*:Don’t care  
Fig.13 Random Read Cycle Timing  
○Sequential Read  
･If the Master does not transfer an Acknowledge and does not generate a STOP condition during the current Read  
operation, the BR24C21/F/FJ/FV continues to output the next address data in sequence. For Read operations, all bits  
in the address counter are incremented, allowing the entire array to be read during a single operation. When the  
counter reaches the top of the array, it will “roll over” to the bottom of the array and continue to transmit data.  
･If the Master does not acknowledge the transmission but does generate a STOP condition, at this point the device  
discontinues transmission.  
･The sequential Read operation can be performed with both Current Read and Random Read.  
S
R
S
T
O
P
T
A
R
T
E
A
D
SLAVE  
ADDRESS  
DATA(n)  
DATA(n+x)  
SDA  
LINE  
1
0
1
0
*
*
*
D7  
D0  
D7  
D0  
R
/
W K  
A
C
A
C
K
A
C
K
A
C
K
*:Don’t care  
Fig.14 Sequential Read Cycle Timing  
(Current Read)  
www.rohm.com  
© 2011 ROHM Co., Ltd. All rights reserved.  
2011.08 - Rev.C  
7/22  
1...45678910...23

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