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BU9882FV-WE2

更新时间： 2024-02-09 21:38:53

品牌	Logo	应用领域
罗姆 - ROHM		存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
23页	647K
描述
EDID Memory (For display)

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技术参数
数据手册

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BU9882FV-WE2 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	ROHS COMPLIANT, SSOP-14	针数：	14
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	1.45
Is Samacsys：	N	最大时钟频率 (fCLK)：	0.4 MHz
JESD-30 代码：	R-PDSO-G14	长度：	5 mm
内存密度：	2048 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端口数量：	2	端子数量：	14
字数：	256 words	字数代码：	256
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	256X8
封装主体材料：	PLASTIC/EPOXY	封装代码：	LSSOP
封装等效代码：	TSSOP14,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3/5 V
认证状态：	Not Qualified	座面最大高度：	1.25 mm
串行总线类型：	I2C	最大待机电流：	0.000005 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	4 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm	最长写入周期时间 (tWC)：	10 ms
Base Number Matches：	1

BU9882FV-WE2 数据手册

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,

BU9882-W,BU9882F-W,BU9882FV-W

Technical Note

●Bi-directional mode

○Bi-directional Mode and Recovery Function

・The BR24C21/F/FJ/FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid High to Low

transition at the SCL pin, while the state of SDA is at high-impedance.

・After a valid high to low transition on the SCL pin, the BR24C21/F/FJ/FV begins to count the VCLK clock. If the VCLK

counter reaches 128 clocks without the command for Bi-directional Mode, the device reverts to Transmit-Only Mode

(Recovery function). The VCLK counter is reset by providing a valid high to low transition at the SCL pin. After reversal

to Transmit-Only Mode the device begins to output data (00h address data) with the 129th rising clock edge of VCLK.

・If the BR24C21/F/FJ/FV is switched from Transmit-Only Mode and receives the command for Bi-directional

Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only Mode. (Power down is the only

way to revert to Transmit-Only Mode.) Unless the input device code is “1010”, the device does not respond with an

Acknowledge. If the VCLK counter reaches 128 clocks afterwards, it is possible to revert to Transmit-Only Mode for

Recovery function. If the Master generates a STOP condition during the Slave address, before an Acknowledge is input,

it is possible to revert to Transmit-Only Mode.

・When the device is switched from Transmit-Only Mode to Bi-direction Mode, the period of tVHZ needs to be held.

B i - d i r e c t i o n a l

Bi-directional

B i - d i r e c t i o n a l

Transmit-oOnly

Bi-directional

B i - d i r e c t i o n a l

p a r m a n e n t l y

parmanently

T r a n s m i t - o n l y

T r a nTr

smit

n l y

T r a n s m i t - o n l y

Transmit-only

T r a n s i t i o n M o d e w i t h p o s s i b i l i t y

Transition Mode with possibility to

ＭＯＤＥ

t o r e t u n e t o T r a n s m i t - O n l y M o d e

return to Transmit-Only Mode

ｎ＜１２８

ｎ

１２７１２８１２９

１

２

３

４

１

２

ＶＣＬＫ

ＳＣＬ

ＳＤＡ

ＶＣＬＫ

ＳＣＬ

ＳＤＡ

A D D R E S S 0 0 h

ADDRESS 00h

ｔＶＨＺ

Ｄ７Ｄ６Ｄ５Ｄ４

Ｓ

１

０

１

０

＊

Ｒ/ＷＡＣＫ

*Don’t care

Fig.8 Recovery Mode

Fig.9 Mode Change

○Bi-directional Mode

START Condition

・All commands are proceeded by the START condition, which is a High to Low transition of SDA when SCL is High.

・The BR24C21/F/FJ/FV continuously monitors the SDA and SCL lines for the START condition and will not respond to

any commands until this condition has been met.

(See Fig. 3 Synchronous Data Timing)

STOP Condition

・All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is High.

・The STOP condition causes the internal write cycle to write data into the memory array after a write sequence.

・The STOP condition is also used to place the device into standby power mode after read sequences.

・A STOP condition can only be issued after the transmitting device has released the bus.

(See Fig.3 Synchronous Data Timing)

Device Addressing

・Following the START condition, the Master outputs the device address of the Slave to be accessed. The most

significant four bits of Slave address are the “device type indentifier,” For the BR24C21/F/FJ/FV this is fixed as

“1010.”

・The next three bits of the slave address are inconsequential.

・The last bit of the stream determines the operation to be performed. When set to “1”, a READ operation is selected.

When set to “0”, a WRITE operation is initiated.

R/W set to "0" ・・・・・・・・ WRITE (This bit is also set to "0" for random read operation)

R/W set to "1" ・・・・・・・・ READ

R/W

1010

＊

＊：Don’t care

○Write Protect Function

・Write Enable (VCLK)

When using the BR24C21/F/FJ/FV in Bi-directional Mode, the VCLK pin can be used as a write enable pin. Setting

VCLK High allows normal write operations, while setting VCLK low prevents writing to any location in the array.

(See Fig.5 Write Enable Timing)

Changing VCLK from High to Low during the self-timed program operation will not halt programming of the device.

www.rohm.com

2011.08 - Rev.C

5/22

1 2 3 456 7 8...23

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