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BU9882

更新时间： 2024-01-31 11:54:58
品牌 Logo 应用领域
罗姆 - ROHM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数 文件大小 规格书
17页 812K
描述
EEPROM, PDIP14, DIP-14

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BU9882 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP14,.3针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.83
最大时钟频率 (fCLK)：0.4 MHzJESD-30 代码：R-PDIP-T14
JESD-609代码：e3/e2长度：19.4 mm
内存密度：2048 bit内存集成电路类型：EEPROM
内存宽度：8功能数量：1
端口数量：2端子数量：14
字数：256 words字数代码：256
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256X8
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：SERIAL
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：4.55 mm
串行总线类型：I2C最大待机电流：0.000005 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：4 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN/TIN COPPER端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：10宽度：7.62 mm
最长写入周期时间 (tWC)：10 ms

BU9882 数据手册

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○Current Read  
The BR24C21/F/FJ/FV contains an internal address counter which maintains the address of the last word accessed,  
incremented by one. If the last accessed address is address “n” in a Read operation, the next Read operation will  
access data from address “n+1” and increment the current address counter. If the last accessed address is address  
”n” in a Write operation, the next Read operation will access data from address “n”. If the Master does not transfer an  
Acknowledge, but does generate a STOP condition, the current address read operation will only provide a single byte of  
data. At this point, the device discontinues transmission.  
(See Fig.14 Sequential Read Cycle Timing）  
S
R
E
A
D
S
T
O
P
T
A
R
T
SLAVE  
ADRESS  
DATA  
SDA  
LINE  
＊ ＊ ＊  
1
0
1
0
D7  
D0  
R
A
C
K
A
C
K
/
W
*:Don’t care  
Fig.12 Current Read Cycle Timing  
○Random Read  
The Random read operation allows the Master to access any memory location. This operation involves a two-step  
process. First, the Master issues a Write command that includes the START condition and the Slave address field (with  
R/W set to “0”) followed by the word address of the word to be read. This procedure sets the internal address counter of  
the BR24C21/F/FJ/FV to the desired address. After the word address Acknowledge is received by the Master, the  
Master immediately re-issues a START condition followed by the Slave address field with R/W set to “1.” The device will  
respond with an Acknowledge and then transmit the 8-data bits stored at the addressed location. If the Master does not  
acknowledge the transmission but does generate the STOP condition, the IC will discontinue transmission.  
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE  
ADDRESS  
WORD  
ADDRESS（ｎ）  
SLAVE  
ADDRESS  
DATA(n)  
SDA  
LINE  
WA  
0
WA  
6
1
0
1
0
*
*
*
*
1
0
1
0
*
*
*
D7  
D0  
A
C
K
R
/
W K  
A
C
A
C
K
R
/
W K  
A
C
*:Don’t care  
Fig.13 Random Read Cycle Timing  
○Sequential Read  
･If the Master does not transfer an Acknowledge and does not generate a STOP condition during the current Read  
operation, the BR24C21/F/FJ/FV continues to output the next address data in sequence. For Read operations, all bits  
in the address counter are incremented, allowing the entire array to be read during a single operation. When the  
counter reaches the top of the array, it will “roll over” to the bottom of the array and continue to transmit data.  
･If the Master does not acknowledge the transmission but does generate a STOP condition, at this point the device  
discontinues transmission.  
･The sequential Read operation can be performed with both Current Read and Random Read.  
S
R
S
T
O
P
T
A
R
T
E
A
D
SLAVE  
ADDRESS  
DATA(n)  
DATA(n+x)  
SDA  
LINE  
1
0
1
0
*
*
*
D7  
D0  
D7  
D0  
R
/
W K  
A
C
A
C
K
A
C
K
A
C
K
*:Don’t care  
Fig.14 Sequential Read Cycle Timing  
(Current Read)  
6/16  
1...3456789...17

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