Datasheet > BU9795AFV-LBE2

BU9795AFV-LBE2

更新时间： 2024-02-05 14:04:58

品牌	Logo	应用领域
罗姆 - ROHM		/
页数	文件大小	规格书
29页	862K
描述
Standard LCD Segment Drivers

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BU9795AFV-LBE2 数据手册

Daattaasshheeeett

BU9795AFV-LB

MAX 108 segments (SEG27×COM4)

Write display data and transfer method

<BU9795AFV-LB>

This LSI has Display Data RAM (DDRAM) of 27×4=108bit.

As SEG0, SEG1, SEG2, SEG3, SEG31, SEG32, SEG33, SEG34 are not output, these address will be dummy

address.

The relationship between data input and display data, DDRAM data and address are as follows.

Command

0000000

v x y

…

Dummy data

Display Data

8 bit data will be stored in DDRAM. The address to be written is the address specified by ADSET command, and the

address is automatically incremented in every 4bit data.

Data can be continuously written in DDRAM by transmitting Data continuously.

(When RAM data is written successively after writing RAM data to 22h (SEG34), the address is returned to 00h (SEG0)

by the auto-increment function.

Dummy data

DDRAM address

06h 07h ・・・・・・・ 1Eh 1Fh

00h

01h

02h

03h

04h

05h

20h

21h

22h

COM0

COM1

COM2

COM3

BIT

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 ・・・・・・・ SEG30 SEG31 SEG32 SEG33 SEG34

As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes CSB=“L”→”H” before

4bits data transfer.

Command

RAM write

CSB

SCL

Address set

D7 D6 D5 D4 D3 D2 D1 D0

Internal signal

RAM write

Address00h

Address01h

Address02h

Write data will be

canceled, when CSB='H'

without

RAM write (Every 4bit data)

4bit data transfer.

Command

RAM write

CSB

SCL

Address set

D7 D6 D5 D4 D3 D2 D1 D0

Internal signal

RAM write

Address00h

Address21h

Address22h

Address00h

Return to address "0"

by automatically

increment.

Figure 9. BU9795AFV-LB Data Transfer Format

www.rohm.com

TSZ02201-0P4P0D300510-1-2

26.Feb.2014 Rev.002

7/26

TSZ22111･15･001

1...4 5 678 9 10...29

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