BU7963GUW

更新时间： 2024-01-21 19:18:51

品牌	Logo	应用领域
罗姆 - ROHM		数据传输
页数	文件大小	规格书
20页	426K
描述
Data rate 1350Mbps RGB Interface

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BU7963GUW 数据手册

Technical Note

BU7963GUW

Table 4. Parallel Data Interface

Functions

Parallel Data Interface

29-pin

Equivalent

Schematic

Name

Width

Level

I/O

Shutdown

PCLK

CMOS

PCLK interface.

Input

‘L’

PD[26:0]

CKD

Parallel data interface.

Output of PCLK detection result.

‘L’: clock stop.

‘H’: clock detect.

Table 5. Control

Functions

Control

8-pin

Equivalent

Schematic

Name

Width

Level

I/O

Shutdown

Input

Shutdown pin.

‘L’: shutdown.

XSD

CMOS

‘H’: normal operation.

Selection of the number of data channel and

the data format.

＊Refer to "Selection of the number of

MSDL3 channels".

＊Set the same number of data channel

between the TX device and the RX device.

LS0

LS1

CMOS

Input

Selection of MSDL3 pins assignment.

‘L’: Default matrix.

‘H’: Flipped matrix.

RVS

CMOS

Input

PLL_BW

POL_PCLK

TEST0

TEST1

Selection of PLL bandwidth.

Selection of input clock polarity.

‘L’: sample parallel data at falling.

‘H’: sample parallel data at rising.

Test mode pin.

‘L’: normal mode.

‘H’: test mode.

Must be ‘L.’

Pull

down

Input

MSVDD

DVDD

Fig.4. Equivalent Schematics

www.rohm.com

2010.04 - Rev.A

6/19

1...3 4 567 8 9...20

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