Datasheet > BU-61581

BU-61581

更新时间： 2024-11-13 23:36:07

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
44页	563K
描述
MIL-STD-1553 Components \|ACE

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中文翻译

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数据手册

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BU-61581 数据手册

BU-65170/61580 and BU-61585

MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,

ADVANCED COMMUNICATION ENGINE (ACE)

ACE User’s Guide

FEATURES

Also Available

Fully Integrated MIL-STD-1553

Interface Terminal

•

DESCRIPTION

DDC's BU-65170, BU-61580 and configured as 12K x 16 or 8K x 17.

BU-61585 Bus Controller / Remote The 8K x 17 RAM feature provides

Flexible Processor/Memory

Interface

•

Terminal

Monitor

Terminal capability for memory integrity check-

(BC/RT/MT)

A d v a n c e d ing by implementing RAM parity gen-

Communication Engine (ACE) termi- eration and verification on all access-

nals comprise a complete integrated es. To minimize board space and

interface between a host processor “glue” logic, the ACE provides ultimate

and a MIL-STD-1553 A and B or flexibility in interfacing to a host

Standard 4K x 16 RAM and

Optional 12K x 16 or 8K x 17 RAM

Available

STANAG 3838 bus.

processor and internal/external RAM.

Optional RAM Parity

Generation/Checking

•

The ACE series is packaged in a 1.9 - The advanced functional architecture

square-inch, 70-pin, low-profile, of the ACE terminals provides soft-

cofired MultiChip Module (MCM) ware

ceramic package that is well suited for Advanced Integrated Multiplexer (AIM)

applications with stringent height series hybrids, while incorporating a

compatibility

DDC's

Automatic BC Retries

•

Programmable BC Gap Times

BC Frame Auto-Repeat

requirements.

multiplicity of architectural enhance-

ments. It allows flexible operation

while off-loading the host processor,

ensuring data sample consistency,

and supports bulk data transfers.

The BU-61585 ACE integrates dual

transceiver, protocol, memory man-

agement, processor interface logic,

and a total of 12K words of RAM in a

Flexible RT Data Buffering

Programmable Illegalization

Selective Message Monitor

Simultaneous RT/Monitor Mode

choice of DIP or flat pack packages. The ACE hybrids may be operated at

The BU-61585 requires +5 V power either 12 or 16 MHz. Wire bond

and either -15 V or -12 V power. options allow for programmable RT

address (hardwired is standard) and

The BU-61585 internal RAM can be external transmitter inhibit inputs.

TX/RX_A

SHARED

RAM

TRANSCEIVER

CH. A

DATA

BUFFERS

PROCESSOR

D15-D0

DATA BUS

TX/RX_A

TX/RX_B

DUAL

ENCODER/DECODER,

MULTIPROTOCOL

AND

MEMORY

MANAGEMENT

ADDRESS

BUFFERS

PROCESSOR

ADDRESS BUS

A15-A0

ADDRESS BUS

TRANSCEIVER

CH. B

TX/RX_B

TRANSPARENT/BUFFERED, STRBD, SELECT,

RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,

MSB/LSB/DTGRT

PROCESSOR

AND

MEMORY

INTERFACE

LOGIC

PROCESSOR

AND

MEMORY

CONTROL

RT ADDRESS

RTAD4-RTAD0, RTADP

INCMD

IOEN, MEMENA-OUT, READYD

ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,

8/16-BIT/DTREQ, POLARITY_SEL/DTACK

INT

INTERRUPT

REQUEST

CLK_IN, TAG_CLK,

MSTCLR,SSFLAG/EXT_TRG

MISCELLANEOUS

* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY

FIGURE 1. ACE BLOCK DIAGRAM

1992, 1999 Data Device Corporation

12 3 4 5 6 7...44

中文翻译

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与BU-61581相关器件

型号	品牌	获取价格	描述	数据表
BU-61581G1-100	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G1-110	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G1-120	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G1-200	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G1-300	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G2-100	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G2-110	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G2-120	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G2-200	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
BU-61581G2-300	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU

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