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BSC9132NXE7KNKB

更新时间: 2024-11-13 21:07:47
品牌 Logo 应用领域
恩智浦 - NXP 双倍数据速率外围集成电路
页数 文件大小 规格书
145页 1947K
描述
QorIQ Qonverge SoC, 2x1GHz StarCore DSP, 2x1GHz e500 CPU, MAPLE-B2P accelerator, DDR3, SEC, -40-105C

BSC9132NXE7KNKB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:TransferredReach Compliance Code:compliant
ECCN代码:5A002.AHTS代码:8542.31.00.01
风险等级:5.64JESD-609代码:e1
湿度敏感等级:3峰值回流温度(摄氏度):245
技术:CMOS端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
处于峰值回流温度下的最长时间:30uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

BSC9132NXE7KNKB 数据手册

 浏览型号BSC9132NXE7KNKB的Datasheet PDF文件第2页浏览型号BSC9132NXE7KNKB的Datasheet PDF文件第3页浏览型号BSC9132NXE7KNKB的Datasheet PDF文件第4页浏览型号BSC9132NXE7KNKB的Datasheet PDF文件第5页浏览型号BSC9132NXE7KNKB的Datasheet PDF文件第6页浏览型号BSC9132NXE7KNKB的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: BSC9132  
Rev. 1, 08/2014  
BSC9132  
BSC9132 QorIQ Qonverge  
Multicore Baseband  
Processor  
FC-PBGA–780  
23 mm x 23 mm  
The following list provides an overview of the feature set:  
• Two high-performance 32-bit e500 cores built on Power  
Architecture® technology:  
– TCP/IP acceleration, quality of service, and  
classification capabilities  
– IEEE Std 1588™ support  
– Supports SGMII interfaces  
– 36-bit physical addressing  
• High-speed interfaces supporting the following  
multiplexing options:  
– Double-precision floating-point support  
– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data  
cache  
– Enhanced hardware and software debug support  
– 800 Mhz/1 GHz/1.2 GHz clock frequency  
– 512-Kbyte L2 cache with ECC; also configurable as  
SRAM and stashing memory  
– One PCI Express interface with 5G support  
– Four lanes of high-speed serial interfaces (SerDes) to be  
shared between PCI Express, SGMII, and CPRI  
• High-speed USB controller (USB 2.0)  
– Host and device support  
– Enhanced host controller interface (EHCI)  
– ULPI interface  
• Two SC3850 core subsystems; each core connects to the  
following:  
• Enhanced secure digital (SD/MMC) host controller  
(eSDHC)  
– 32 Kbyte 8-way level 1 data/instruction cache  
(L1 Dcache/ICache)  
• Integrated Flash controller (IFC), supporting NAND,  
NOR, and general ASIC  
– 512 Kbyte 8-way level 2 unified instruction/data cache  
(L2 cache/M2 memory)  
• Two TDM interfaces  
– Memory management unit (MMU)  
– Enhanced programmable interrupt controller (EPIC)  
– Debug and profiling unit (DPU)  
• Antenna interface controller (AIC), supporting four  
industry standard JESD/four custom parallel RF interfaces  
(three dual and one single port) and a 2-lane CPRI interface  
• Universal Subscriber Identity Module (USIM) interface  
– Facilitates communication to SIM cards or Eurochip  
pre-paid phone cards  
– Two 32-bit quad timers  
• 32 Kbytes of shared M3 memory  
• Multi Accelerator Platform Engine for Pico Base Station  
Baseband Processing (MAPLE-B2P)  
• Two enhanced serial peripheral interfaces (eSPI)  
• Programmable interrupt controller (PIC) compliant with  
OpenPIC standard  
– Supports variable sizes in Fourier Transforms,  
Convolution, Filtering, Turbo, Viterbi, Chiprate, MIMO  
– Consists of accelerators for UMTS chip rate processing,  
LTE UP/DL channel processing, Matrix Inversion  
operations, and CRC algorithms  
• Two DMA controllers  
– 4-channel DMA on Power Architecture side  
– 32 unidirectional channels, providing up to 16  
memory-to-memory channels on DSP side  
• Two DDR3/DDR3L SDRAM memory controllers support  
32-bit with ECC  
• Integrated security engine (ULE CAAM)  
– Protocol support includes DES, AES, RNG, CRC, MDE,  
PKE, SHA, and MD5  
2
• Two I C interfaces  
• Two dual UART (DUART) interfaces  
• 96 general-purpose I/O signals  
• Eight 32-bit timers  
• Secure boot capability  
• Operating temperature (Ta - T ) range: 0–105° C  
• Two enhanced three-speed Ethernet controllers (eTSECs)  
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© 2014 Freescale Semiconductor, Inc. All rights reserved.  

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