Very Low Power CMOS SRAM
256K X 8 bit
BS62LV2006
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
n DESCRIPTION
ŸWide VCC operation voltage : 2.4V ~ 5.5V
ŸVery low power consumption :
The BS62LV2006 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.1uA at 3.0V/25OC and maximum access time of 55ns at
3.0V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
VCC = 3.0V Operation current : 23mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.1uA (Typ.) at 25OC
VCC = 5.0V Operation current : 55mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 0.6uA (Typ.) at 25OC
ŸHigh speed access time :
-55
55ns (Max.) at VCC : 3.0~5.5V
-70
70ns (Max.) at VCC : 2.7~5.5V
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE2, CE1 and OE options
ŸThree state outputs and TTL compatible
ŸFully static operation
The BS62LV2006 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV2006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, 8mmx20mm TSOP and
36-ball BGA package.
ŸData retention supply voltage as low as 1.5V
n POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
VCC=5V
10MHz
VCC=3V
10MHz
VCC=5.0V VCC=3.0V
1MHz
9mA
fMax.
1MHz
fMax.
BS62LV2006DC
BS62LV2006HC
BS62LV2006SC
BS62LV2006STC
BS62LV2006TC
BS62LV2006HI
BS62LV2006SI
BS62LV2006STI
BS62LV2006TI
DICE
BGA-36-0608
SOP-32
Commercial
6.0uA
20uA
0.7uA
2.0uA
29mA
30mA
53mA
1.5mA
9mA
22mA
+0OC to +70OC
STSOP-32
TSOP-32
BGA-36-0608
SOP-32
Industrial
10mA
55mA
2mA
10mA
23mA
-40OC to +85OC
STSOP-32
TSOP-32
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A7
A12
A14
A16
A17
A15
A11
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
Address
Input
Memory Array
10
1024
Row
Decoder
BS62LV2006TC
BS62LV2006TI
BS62LV2006STC
BS62LV2006STI
1024 x 2048
9
Buffer
10
11
12
13
14
15
16
A9
A13
A6
A5
A4
A1
A2
A3
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Data
Input
Buffer
8
8
8
Column I/O
Write Driver
Sense Amp
1
2
3
4
5
6
8
Data
Output
Buffer
A17
A16
A14
A12
A7
1
32
31
30
29
28
27
26
VCC
256
A
B
C
D
E
F
A0
A1
CE2
A3
A6
A8
2
A15
CE2
WE
A13
A8
3
Column Decoder
DQ4
DQ5
VSS
VCC
DQ6
DQ7
A9
A2
WE
NC
A4
A5
A7
DQ0
DQ1
VCC
VSS
DQ2
DQ3
A14
4
5
8
CE2
CE1
WE
A6
6
A5
7
A9
Control
Address Input Buffer
A4
8
BS62LV2006SC 25
BS62LV2006SI
A11
OE
OE
A3
9
24
23
22
21
20
19
18
17
VCC
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
A6 A5 A10 A4 A3 A2 A1 A0
A1
NC
CE1
A11
A17
A16
A12
A0
DQ0
DQ1
DQ2
GND
G
H
OE
A15
A13
A10
36-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV2006
Revision 1.3
May. 2006
1