Ultra Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
BSI
BS616UV8020
DESCRIPTION
FEATURES
• Ultra low operation voltage : 1.8 ~3.6V
• Ultra low power consumption :
The BS616UV8020 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 1.8V to 3.6V supply voltage.
Vcc = 2.0V C-grade: 15mA (Max.) operating current
I-grade : 20mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.4uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), and active LOW chip enable1(CE1), an active LOW
output enable(OE) and three-state output drivers.
-70
-10
70ns (Max.) at Vcc=2V
100ns (Max.) at Vcc=2V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616UV8020 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV8020 is available in 48-pin BGA type.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
OPERATING
Vcc
PRODUCT FAMILY
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
RANGE
Vcc=2 V
Vcc=2V
Vcc=3V
Vcc=2V
Vcc=3V
BS616UV8020BC
BS616UV8020BI
+0 O C to +70O
-40 O C to +85O
C
C
1.8V ~ 3.6V
1.8V ~ 3.6V
70 / 100
70 / 100
2uA
4uA
3uA
6uA
15mA
20mA
20mA
25mA
BGA-48-0810
BGA-48-0810
BLOCK DIAGRAM
PIN CONFIGURATIONS
A15
A14
A13
1
2
3
4
5
6
A12
A11
A10
A9
Address
Input
LB
OE
A0
A1
A2
CE2
D0
A
B
C
D
E
F
22
2048
Row
Decoder
Memory Array
2048 x 4096
Buffer
D8
D9
UB
D10
D11
D12
D13
CI.O
A8
A3
A5
A4
A6
A7
CE1
D1
D3
D4
D5
A8
A17
A7
A6
D2
4096
Data
16(8)
16(8)
Column I/O
Input
D0
A17
Buffer
VSS
VCC
VSS
D6
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16(8)
16(8)
256(512)
Column Decoder
Data
VSS A16
VCC
D14
Output
Buffer
D15
A14
A12
A9
A15
A13
A10
CE1
CE2
WE
OE
UB
16(18)
D7
Control
Address Input Buffer
G
H
D15
A18
WE
LB
CIO
A16 A0 A1 A2 A3 A4
A5 A18
(SAE)
A11
SAE.
Vdd
Vss
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.4
April 2002
R0201-BS616UV8020
1