Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Dual CE Pins)
BSI
BS616LV8016
FEATURES
• Fully static operation
• Wide Vcc operation voltage : 2.4~5.5V
• Very low power consumption :
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 75mA (@55ns) operating current
I -grade: 76mA (@55ns) operating current
C-grade: 60mA (@70ns) operating current
I -grade: 61mA (@70ns) operating current
8.0uA (Typ.) CMOS standby current
• High speed access time :
DESCRIPTION
The BS616LV8016 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.5uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
-55
-70
The BS616LV8016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8016 is available in 48-pin BGA package.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
OPERATING
TEMPERATURE
Vcc
RANGE
(ICCSB1, Max)
(ICC, Max)
PRODUCT FAMILY
PKG TYPE
55ns : 3.0~5.5V
70ns : 2.7~5.5V
Vcc=3V
Vcc=5V
70ns
Vcc=3V
5uA
Vcc=5V
55uA
uA
70ns
BS616LV8016FC
BS616LV8016FI
+0 O C to +70O
-40O C to +85O
C
C
2.4V ~ 5.5V
2.4V ~ 5.5V
55 / 70
55 / 70
24mA
60mA
61mA
BGA-48-0912
BGA-48-0912
10uA 110
25mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
A4
A3
A2
1
2
3
4
5
6
A1
A0
Address
Input
A
B
C
D
LB
OE
A0
A1
A2
CE2
22
2048
A17
A16
Row
Decoder
Memory Array
2048 x 4096
Buffer
D8
D9
UB
A3
A5
A4
A6
CE1
D1
D0
D2
A15
A14
A13
A12
D10
4096
Data
Input
Buffer
16
16
Column I/O
D0
VSS D11
VCC D12
A17
A7
D3
D4
VCC
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16
256
A16
A15
A13
A10
Data
Output
Buffer
VSS
A14
VSS
D6
E
F
16
Column Decoder
D15
D5
D14
D15
A18
D13
CE2
16
CE1
WE
OE
WE
A11
D7
A12
A9
G
H
N.C
A8
Control
Address Input Buffer
UB
LB
A11 A10 A9 A8 A7
A6 A5 A18
NC
Vcc
Vss
48-Ball CSP top View
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.1
R0201-BS616LV8016
1
Jan.
2004