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BS616LV4017AIG70 PDF预览

BS616LV4017AIG70

更新时间: 2024-02-22 20:57:32
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
11页 242K
描述
Very Low Power CMOS SRAM 256K X 16 bit

BS616LV4017AIG70 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA48,6X8,30
针数:48Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.83最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B48
长度:8 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:48字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.0000015 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.065 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:6 mmBase Number Matches:1

BS616LV4017AIG70 数据手册

 浏览型号BS616LV4017AIG70的Datasheet PDF文件第2页浏览型号BS616LV4017AIG70的Datasheet PDF文件第3页浏览型号BS616LV4017AIG70的Datasheet PDF文件第4页浏览型号BS616LV4017AIG70的Datasheet PDF文件第5页浏览型号BS616LV4017AIG70的Datasheet PDF文件第6页浏览型号BS616LV4017AIG70的Datasheet PDF文件第7页 
Very Low Power CMOS SRAM  
256K X 16 bit  
BS616LV4017  
Pb-Free and Green package materials are compliant to RoHS  
„ FEATURES  
„ DESCRIPTION  
y Wide VCC operation voltage : 2.4V ~ 5.5V  
y Very low power consumption :  
The BS616LV4017 is a high performance, very low power CMOS  
Static Random Access Memory organized as 262,144 by 16 bits and  
operates form a wide range of 2.4V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both  
high speed and low power features with maximum CMOS standby  
current of 4/20uA at Vcc=3/5V at 85OC and maximum access time of  
55/70ns.  
VCC = 3.0V  
Operation current : 27mA (Max.) at 55ns  
2mA (Max.) at 1MHz  
Standby current : 2/4uA (Max.) at 70/85OC  
Operation current : 65mA (Max.) at 55ns  
10mA (Max.) at 1MHz  
VCC = 5.0V  
Standby current : 10/20uA (Max.) at 70/85OC  
y High speed access time :  
Easy memory expansion is provided by an active LOW chip enable  
(CE) and active LOW output enable (OE) and three-state output  
drivers.  
The BS616LV4017 has an automatic power down feature, reducing  
the power consumption significantly when chip is deselected.  
The BS616LV4017 is available in DICE form, JEDEC standard  
44-pin TSOP II and 48-ball BGA package.  
-55  
-70  
55ns(Max.) at VCC=3.0~5.5V  
70ns(Max.) at VCC=2.7~5.5V  
y Automatic power down when chip is deselected  
y Easy expansion with CE and OE options  
y I/O Configuration x8/x16 selectable by LB and UB pin.  
y Three state outputs and TTL compatible  
y Fully static operation  
y Data retention supply voltage as low as 1.5V  
„ POWER CONSUMPTION  
POWER DISSIPATION  
Operating  
STANDBY  
PRODUCT  
FAMILY  
OPERATING  
PKG TYPE  
(ICCSB1, Max)  
(ICC, Max)  
TEMPERATURE  
VCC=5.0V  
10MHz  
VCC=3.0V  
10MHz  
VCC=5.0V VCC=3.0V  
1MHz  
9mA  
fMax.  
1MHz  
fMax.  
BS616LV4017DC  
BS616LV4017AC  
BS616LV4017EC  
BS616LV4017AI  
BS616LV4017EI  
DICE  
Commercial  
10uA  
20uA  
2.0uA  
4.0uA  
39mA  
40mA  
63mA  
1.5mA  
14mA  
15mA  
26mA  
BGA-48-0608  
TSOP II-44  
BGA-48-0608  
TSOP II-44  
+0OC to +70OC  
Industrial  
10mA  
65mA  
2mA  
27mA  
-40OC to +85OC  
„ PIN CONFIGURATIONS  
„ BLOCK DIAGRAM  
A4  
1
44  
A5  
A3  
2
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A6  
A2  
3
A7  
A1  
4
OE  
A12  
A11  
A10  
A0  
5
UB  
CE  
6
LB  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
VSS  
DQ4  
DQ5  
DQ6  
DQ7  
WE  
A17  
A16  
A15  
A14  
A13  
7
DQ15  
DQ14  
DQ13  
DQ12  
VSS  
VCC  
DQ11  
DQ10  
DQ9  
DQ8  
NC  
8
A9  
A8  
A5  
A6  
A7  
A4  
A3  
Address  
Input  
1024  
Memory Array  
10  
9
Row  
Decoder  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
BS616LV4017EC  
BS616LV4017EI  
Buffer  
1024 x 4096  
4096  
A8  
A9  
DQ0  
.
.
.
.
.
.
Data  
16  
Column I/O  
16  
A10  
A11  
A12  
Input  
.
.
.
.
.
.
Buffer  
Write Driver  
Sense Amp  
16  
1
2
3
4
5
6
16  
Data  
Output  
Buffer  
256  
A
B
C
D
E
F
LB  
D8  
OE  
A0  
A1  
A2  
NC  
D0  
Column Decoder  
DQ15  
UB  
D10  
D11  
D12  
D13  
NC  
A3  
A5  
A4  
A6  
CE  
D1  
8
CE  
WE  
OE  
UB  
LB  
D9  
D2  
Address Input Buffer  
Control  
VSS  
VCC  
D14  
D15  
NC  
A17  
NC  
A14  
A12  
A9  
A7  
D3  
VCC  
VSS  
D6  
A13 A14 A15 A16 A17 A0 A1 A2  
A16  
A15  
A13  
A10  
D4  
VCC  
VSS  
D5  
G
H
WE  
A11  
D7  
A8  
NC  
48-ball BGA top view  
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.  
R0201-BS616LV4017  
Revision  
Oct.  
1.4  
1
2008  

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