Datasheet > BS616LV4011BI

BS616LV4011BI

更新时间： 2022-12-14 13:33:36

品牌	Logo	应用领域
BSI		静态存储器
页数	文件大小	规格书
10页	232K
描述
Very Low Power/Voltage CMOS SRAM 256K X 16 bit

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数据手册

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BS616LV4011BI 数据手册

BSI

BS616LV4011

LOW V_CCDATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

^DR≥ 1.5V

Vcc

CDR

≥

CE Vcc - 0.2V

VIH

KEY TO SWITCHING WAVEFORMS

AC TEST CONDITIONS

Input Pulse Levels

Vcc/0V

5ns

WAVEFORM

INPUTS

OUTPUTS

Input Rise and Fall Times

Input and Output

MUST BE

STEADY

MUST BE

STEADY

Timing Reference Level

0.5Vcc

AC TEST LOADS AND WAVEFORMS

MAY CHANGE

FROM H TO L

WILL BE

CHANGE

Ω

1269

5PF

FROM H TO L

3.3V

MAY CHANGE

FROM L TO H

WILL BE

OUTPUT

CHANGE

FROM L TO H

100PF

INCLUDING

DON T CARE:

CHANGE :

STATE

Ω

1404

JIG AND

SCOPE

JIG AND

SCOPE

ANY CHANGE

PERMITTED

UNKNOWN

FIGURE 1A

FIGURE 1B

DOES NOT

APPLY

CENTER

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

THEVENIN EQUIVALENT

667

Ω

OUTPUT

1.73V

ALL INPUT PULSES

Vcc

GND

10%

90% 90%

10%

→

←

← 5ns

FIGURE 2

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70^oC , Vcc = 3.0V )

READ CYCLE

JEDEC

PARAMETER

NAME

BS616LV4011-70

MIN. TYP. MAX.

BS616LV4011-10

MIN. TYP. MAX.

PARAMETER

NAME

DESCRIPTION

Read Cycle Time

UNIT

t_AVAX

t_AVQV

t_ELQV

t_BA

t_GLQV

t_ELQX

t_BE

t_GLQX

t_EHQZ

t_BDO

t_RC

t_AA

100

Address Access Time

t_ACS

t_BA(1)

t_OE

t_CLZ

t_BE

t_OLZ

t_CHZ

t_BDO

t_OHZ

Chip Select Access Time

(CE)

Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

(LB,UB)

(CE)

(LB,UB)

(CE)

(LB,UB)

t_GHQZ

t_AXOX

t_OH

Output Disable to Address Change

NOTE :

1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.

Revision 2.4

April 2002

R0201-BS616LV4011

1 2 345 6 7...10

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