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BREAKING

更新时间： 2024-11-08 23:35:43

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其他 - ETC		光电二极管
页数	文件大小	规格书
3页	20K
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Breaking through the 1 Mbyte Address Barrier Application Note? 17.3KB (PDF)

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Breaking Through the 1 MByte Address Barrier

Using the Am186ES Microcontroller

The x86 architecture has come to dominate the microprocessor landscape as the most successful architecture in the

world. The 186 is the 16-bit microcontroller version of the x86 architecture and it has had similar success in the 16-bit

embedded market. New versions of the popular 186 have provided more performance, such as the Am186ES

microcontroller that provides 5.35 Dhrystone 2.1 MIPS using 70 ns memory. One area that still provides a barrier to

some applications is the 1 MByte linear address range of the 186. This is the same 1 MByte address range of the

original IBM PC. Breaking this 1 MByte address range is not as easy as setting a compiler switch, but it can be done

with a little software planning. Using the programmable I/O and the unified middle chip select capability of the Am186ES

microcontroller, this greater than 1 MByte address range can be implemented directly to the memories with no external

hardware. The SRAM interface timing, and byte write enables among other system functions are integrated into the

Am186ES microcontroller.

Consider the simple case of a typical system with Flash and SRAM that needs additional data space beyond the 1

MByte boundary. Examples of what this data may be include maps, tables of information or any data base that is

accessed in blocks, rather than randomly throughout the data base. In the case of the map, all the data associated with

a grid would be placed in one segment. A database example may be all the sales made on a certain day.

Figure 1 shows the hardware for an application requiring more than 1 MByte of memory. The upper chip select (UCS)

accesses the Am29F010 Flash containing 256 KBytes of application instructions, interrupt service routines and data that

must remain available for subroutines (for example, text strings for output). The lower chip select (LCS) accesses to

provide the interrupt vector table, stack space and any other volatile memory requirements. The middle chip select 0

(MCS0) connects to the additional Am29F016 Flash memory and is set for 256 KBytes. The unified middle chip select

capability of the Am186ES means that larger sections of memory can be accessed through the single chip select. The

programmable IO (PIO) act as additional address bits into the Am29F016 Flash memory. In this configuration, there are

256 KBytes of SRAM, 256 KBytes of Flash in the Am29F010 always available, 256 KBytes of address space for other

system requirements and 16 independent Flash segments of 256 KBytes each in the Am29F016 Flash. The total

memory, SRAM and Flash, available is 4.5 MBytes. Obviously, there is still a great deal of flexibility remaining in the

address map to adapt this to a particular embedded application’s requirements. Larger or smaller memories could be

used as needed.

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型号	品牌	获取价格	描述	数据表
BRESD12VP1B2ZA	FOSHAN	获取价格	DFN0603
BRESD12VP1B2ZP	FOSHAN	获取价格	DFN1006-2L
BRESD12VP1B2ZPQ	FOSHAN	获取价格	DFN1006-2L
BRESD18VL1B2ZPQ	FOSHAN	获取价格	DFN1006-2L
BRESD24V0M2B3MAQ	FOSHAN	获取价格	SOT-23
BRESD3V3L1B2Z	FOSHAN	获取价格	DFN0603
BRESD3V3L1B2ZA	FOSHAN	获取价格	DFN0603
BRESD3V3L1B2ZAQ	FOSHAN	获取价格	DFN0603
BRESD3V3L1B2ZP	FOSHAN	获取价格	DFN1006-2L
BRESD3V3L1B2ZPQ	FOSHAN	获取价格	DFN1006-2L

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