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BQ4850YMA-85 PDF预览

BQ4850YMA-85

更新时间: 2024-11-05 22:08:39
品牌 Logo 应用领域
德州仪器 - TI 静态存储器
页数 文件大小 规格书
16页 620K
描述
RTC Module With 512Kx8 NVSRAM

BQ4850YMA-85 数据手册

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bq4850Y  
RTC Module With 512Kx8 NVSRAM  
The clock and alarm registers are  
General Description  
Features  
du a l-por t r ea d/wr it e SRAM loca-  
I n t e gr a t e d S R AM , r e a l-t im e  
clock, crystal, power-fail control  
circuit, and battery  
The bq4850Y RTC Module is a non-  
volatile 4,194,304-bit SRAM organ-  
ized as 524,288 words by 8 bits with  
a n in t egr a l a ccessible r ea l-t im e  
clock.  
tions that are updated once per sec-  
ond by a clock control circuit from  
the internal clock counters. The  
dual-port registers allow clock up-  
dates to occur without interrupting  
n or m a l a ccess t o t h e r est of t h e  
SRAM array.  
Real-Time Clock counts seconds  
through years in BCD format  
The device combines an internal lith-  
ium battery, quartz crystal, clock and  
power-fail chip, and a full CMOS  
SRAM in a plastic 32-pin DIP mod-  
ule. The RTC Module directly re-  
places industry-standard SRAMs and  
also fits into many EPROM and EE-  
PROM sockets without any require-  
ment for special write timing or limi-  
tations on the number of write cycles.  
RAM-like clock access  
The bq4850Y also contains a power-  
fail-detect circuit. The circuit dese-  
lects the device whenever VCC falls  
below tolerance, providing a high de-  
gree of data security. The battery is  
electrically isolated when shipped  
from the factory to provide maxi-  
mum battery capacity. The battery  
remains disconnected until the first  
Pin-compatible with industry-  
standard 512K x 8 SRAMs  
Unlimited write cycles  
10-year minimum data retention  
and clock operation in the absence  
of power  
Automatic power-fail chip dese-  
Registers for the rea l-time clock,  
alarm and other special functions  
are located in registers 7FFF8h–  
7FFFFh of the memory array.  
application of VCC  
.
lect and write-protection  
Soft wa r e clock ca libr a t ion for  
gr e a t e r t h a n ±1 m in u t e p e r  
month accuracy  
Pin Connections  
Pin Names  
A0–A18  
CE  
Address input  
Chip enable  
A
32  
1
V
18  
CC  
A
A
31  
30  
2
3
A
A
16  
14  
15  
17  
4
WE  
A
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
WE  
Write enable  
Output enable  
12  
5
A
A
A
A
A
A
A
13  
7
6
5
4
3
2
OE  
6
A
8
A
9
A
11  
OE  
7
DQ0–DQ7 Data in/data out  
8
9
VCC  
VSS  
+5 volts  
Ground  
10  
11  
12  
13  
14  
15  
16  
A
10  
CE  
DQ  
DQ  
DQ  
DQ  
DQ  
A
1
0
0
A
DQ  
DQ  
DQ  
7
6
5
4
3
1
2
V
SS  
32-Pin DIP Module  
PN485001.eps  
Aug. 1996  
1

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