BQ24704RGER

更新时间： 2025-07-14 06:44:11

品牌	Logo	应用领域
德州仪器 - TI		电源电路电池电源管理电路
页数	文件大小	规格书
31页	1473K
描述
Low Cost, Host-Controlled Li-Ion and Li-Polymer Battery Charger With Low Iq

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BQ24704RGER 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.15	Is Samacsys：	N
可调阈值：	YES	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	S-PQCC-N24	JESD-609代码：	e4
长度：	4 mm	湿度敏感等级：	2
信道数量：	1	功能数量：	1
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1 mm
最大供电电压 (Vsup)：	24 V	最小供电电压 (Vsup)：	5 V
标称供电电压 (Vsup)：	7 V	表面贴装：	YES
温度等级：	AUTOMOTIVE	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm	Base Number Matches：	1

BQ24704RGER 数据手册

bq24704

SLUS838–MAY 2009........................................................................................................................................................................................................ www.ti.com

Table 1. TERMINAL FUNCTIONS – 24-PIN QFN

TERMINAL

DESCRIPTION

NAME

NO.

PVCC

IC power positive supply. Place a 0.1-µF ceramic capacitor from PVCC to PGND pin close to the IC.

Charge enable active-low logic input. LO enables charge. HI disables charge. Connect a 10-kΩ pull-up resistor from

CHGEN to a pull-up supply rail.

CHGEN

Adapter current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide

ACN 2 differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND for

common-mode filtering.

ACN

Adapter current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide

differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.

ACP

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from

adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V.

The I_ADAPTcurrent sense amplifier is active when the ACDET pin voltage is greater than 0.6 V.

ACDET

Adapter current set input. The voltage ratio of ACSET voltage versus VREF voltage programs the input current

regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VREF

to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin.

ACSET

Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the

analog ground plane, and only connect to PGND through the PowerPad underneath the IC.

AGND

VREF

3.3-V regulated voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage

could be used for ratiometric programming of voltage and current regulation.

Charge voltage set input. The voltage ratio of VADJ voltage versus VREF voltage programs the battery voltage

regulation set-point. Program by connecting a resistor divider from VREF to VADJ, to AGND; or, by connecting the

output of an external DAC to VADJ. VADJ connected to REGN programs the default of 4.2 V per cell.

VADJ

Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed

threshold. Connect a 10-kΩ pullup resistor from ACGOOD pin to pullup supply rail.

ACGOOD

ISYNSET

IADAPT

SRSET

Synchronous mode current set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent

11 threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor

current. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).

Adapter current sense amplifier output. IADAPT voltage is 16 times the differential voltage across ACP-ACN. Place a

100-pF or less ceramic decoupling capacitor from IADAPT to AGND.

Charge current set input. The voltage ratio of SRSET voltage versus VREF voltage programs the charge current

13 regulation set-point. Program by connecting a resistor divider from VREF to SRSET to AGND; or by connecting the

output of an external DAC to SRSET pin.

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the

14 BAT pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND close to the IC to

filter high-frequency noise.

BAT

SRN

Charge current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from SRN to SRP to provide

15 differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from SRN pin to AGND for common-mode

filtering.

Charge current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from SRN to SRP to provide

differential-mode filtering. A 0.1-µF ceramic capacitor is placed from SRP pin to AGND for common-mode filtering.

SRP

CELLS

17 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.

Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input

18 current is being limited by reducing the charge current. Connect 10-kΩ pullup resistor from DPMDET to VREF or a

different pullup-supply rail.

DPMDET

PGND

Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source

19 of low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to

AGND through the PowerPad underneath the IC.

LODRV

REGN

20 PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.

PWM low side driver positive 6-V supply output. Connect a 1-µF ceramic capacitor from REGN to PGND, close to the

IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.

PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power

22 MOSFET drain, high-side power MOSFET source, and output inductor). Connect the 0.1-µF bootstrap capacitor from

from PH to BTST.

HIDRV

BTST

23 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

PWM high side driver positive supply. Connect a 0.1-µF bootstrap ceramic capacitor from BTST to PH. Connect a

small bootstrap Schottky diode from REGN to BTST.

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BQ24704RGER 替代型号

型号	品牌	替代类型	描述	数据表
BQ24704RGET	TI	类似代替	Low Cost, Host-Controlled Li-Ion and Li-Polymer Battery Charger With Low Iq

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