BD8255MUV-M
Description of Blocks
■ Serial Peripheral Interface (SPI)
16 bit serial interfaces (SLV, SCLK, SDI, SDO) are provided to perform setting of operations and output levels. SPI
communication is performed while SLV terminal is in Low. SDI data are sent to internal shift register at the rising edge of
SCLK terminal. Shift register data are loaded into 12 bit internal shift register at the rising edge of SLV terminal according to
the address map. Readout operation is performed when readout bit is set to 1. Then state is read out at the falling edge of
SCLK terminal and output to SDO terminal.
◆ Input-Output Timing
Figure 4 shows write/read timing of the serial ports.
Minimum timing of each item is as shown in the table below. In order to prevent increase in delay of SPI input/output timing,
wiring between SLV/SCLK/SDI/SDO and the microcomputer should be as short as possible to minimize the wiring
capacitance.
Symbol
Item
SDI setup time *
SDI hold time *
Setup SLV to SCLK rising edge *
SCLK high pulse width *
SCLK low pulse width *
Setup SCLK rising edge to SLV *
SLV pulse width *
SDO delay time *
SDO hold time *
SDO OFF time *
SCLK frequency
Min
9
9
Typ
Max
-
-
-
-
-
-
-
10
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
A
B
C
D
E
F
G
H
I
-
-
-
-
-
-
-
-
-
-
-
9
10
10
9
15
-
2
-
-
ns
ns
MHz
J
K
20
35
* Guaranteed Design Items
SLV
SCLK
SDI
F
G
E
C
D
A
B
C3
C2
D0
J
H
H
D0
D7
DN-1
DN
SDO
I
Figure 4. SPI Input / Output Timing
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