BelaSigna 300
Audio Processor for Portable Communication Devices
1.0 General Overview
1.1 Introduction
BelaSigna 300 is a DSP-based mixed-signal audio processing system that delivers superior audio clarity without compromising size or
battery life. The processor is specifically designed for monaural portable communication devices requiring high performance audio
processing capabilities and programming flexibility when form-factor and power consumption are key design constraints.
The efficient dual-MAC 24-bit CFX DSP core, together with the HEAR configurable accelerator signal processing engine, high speed
debugging interface, advanced algorithm security system, state-of-the-art analog front end, Class D output stage and much more,
constitute an entire system on a single chip, which enables manufacturers to create a range of advanced and unique products. The
system features a high level of instructional parallelism, providing highly efficient computing capability. It can simultaneously execute
multiple advanced adaptive noise reduction and echo cancellation algorithms, and uses an asymmetric dual-core patented architecture
to allow for more processing in fewer clock cycles, resulting in reduced power consumption.
BelaSigna 300 is supported by a comprehensive suite of development tools, hands-on training, full technical support and a network of
solution partners offering software and engineering services to help speed product design and shorten time to market.
1.2 Key Features
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Flexible DSP-based system: a complete DSP-based, mixed-signal audio system consisting of the CFX core, a fully
programmable, highly cycle-efficient, dual-Harvard architecture 24-bit DSP utilizing explicit parallelism; the HEAR configurable
accelerator for optimized signal processing; and an efficient input/output controller (IOC) along with a full complement of
peripherals and interfaces, which optimize the architecture for audio processing at extremely low power consumption
Excellent audio fidelity: up to 110dB input dynamic range, exceptionally low system noise and low group delay
Ultra-low-power: typically 1-5mA
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Miniature Form Factor: available in a miniature 3.63mm x 2.68mm x 0.92mm (including solder balls) WLCSP package
Multiple audio input sources: four input channels from four input sources can be used simultaneously for multiple
microphones or direct analog audio inputs
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Full range of configurable interfaces: including a fast I2C-based interface for download, debug and general communication, a
highly configurable PCM interface to stream data into and out of the device, a high-speed UART, an SPI port and 5 GPIOs
Integrated A/D converters and powered output: minimize need for external components
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Flexible clocking architecture: supports speeds up to 40MHz
“Smart” power management: including low current standby mode requiring only 0.05mA
Diverse memory architecture: 4864x48-bit words of shared memory between the CFX core and the HEAR accelerator plus
8-Kword DSP core data memory, 12-Kwords of 32-bit DSP core program memory as well as other memory banks
Data security: sensitive program data can be encrypted for storage in external NVRAM to prevent unauthorized parties from
gaining access to proprietary software intellectual property, 128-bit AES encryption
Development tools: interface hardware with USB support as well as a full IDE that can be used for every step of program
development including testing and debugging
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1.3 Contents
1.0 General Overview.................................................................................................................................................................................1
2.0 Mechanical Information and Circuit Design Guidelines ........................................................................................................................2
3.0 Architecture Overview ..........................................................................................................................................................................7
4.0 Figures and Data................................................................................................................................................................................20
5.0 Assembly Information.........................................................................................................................................................................25
6.0 Miscellaneous.....................................................................................................................................................................................28
©2009 SCILLC. All rights reserved.
January 2009 – Rev. 3
Publication Order Number:
BELASIGNA300/D
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