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ATXMEGA128A3-MH PDF预览

ATXMEGA128A3-MH

更新时间: 2024-02-26 21:04:53
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
110页 3392K
描述
8/16-bit AVR XMEGA A3 Microcontroller

ATXMEGA128A3-MH 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliant风险等级:5.31
具有ADC:YES其他特性:IT IS ALSO OPERATES IN 12 MHZ AT 1.6 V
地址总线宽度:位大小:16
最大时钟频率:16 MHzDAC 通道:YES
DMA 通道:YES外部数据总线宽度:
JESD-30 代码:S-XQCC-N64长度:9 mm
I/O 线路数量:50端子数量:64
PWM 通道:YES封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
ROM可编程性:FLASH座面最大高度:1 mm
速度:32 MHz最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:9 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC

ATXMEGA128A3-MH 数据手册

 浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第5页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第6页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第7页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第9页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第10页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第11页 
XMEGA A3  
This concept enables instructions to be executed in every clock cycle. The program memory is  
In-System Re-programmable Flash memory.  
6.3  
6.4  
Register File  
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single  
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-  
ical ALU operation, two operands are output from the Register File, the operation is executed,  
and the result is stored back in the Register File - in one clock cycle.  
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data  
Space addressing - enabling efficient address calculations. One of these address pointers can  
also be used as an address pointer for look up tables in Flash program memory.  
ALU - Arithmetic Logic Unit  
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations  
between registers or between a constant and a register. Single register operations can also be  
executed. Within a single clock cycle, arithmetic operations between general purpose registers  
or between a register and an immediate are executed. After an arithmetic or logic operation, the  
Status Register is updated to reflect information about the result of the operation.  
The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-  
tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy  
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both  
signed and unsigned multiplication and fractional format.  
6.5  
Program Flow  
When the device is powered on, the CPU starts to execute instructions from the lowest address  
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to  
be fetched. After a reset, the PC is set to location ‘0’.  
Program flow is provided by conditional and unconditional jump and call instructions, capable of  
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,  
while a limited number uses a 32-bit format.  
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack  
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited  
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to  
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory  
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can  
easily be accessed through the five different addressing modes supported in the AVR CPU.  
8
8068R–AVR–08/10  

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