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ATXMEGA128A3-MH PDF预览

ATXMEGA128A3-MH

更新时间: 2024-01-11 23:13:49
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
110页 3392K
描述
8/16-bit AVR XMEGA A3 Microcontroller

ATXMEGA128A3-MH 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliant风险等级:5.31
具有ADC:YES其他特性:IT IS ALSO OPERATES IN 12 MHZ AT 1.6 V
地址总线宽度:位大小:16
最大时钟频率:16 MHzDAC 通道:YES
DMA 通道:YES外部数据总线宽度:
JESD-30 代码:S-XQCC-N64长度:9 mm
I/O 线路数量:50端子数量:64
PWM 通道:YES封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
ROM可编程性:FLASH座面最大高度:1 mm
速度:32 MHz最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:9 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC

ATXMEGA128A3-MH 数据手册

 浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第4页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第5页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第6页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第8页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第9页浏览型号ATXMEGA128A3-MH的Datasheet PDF文件第10页 
XMEGA A3  
6. AVR CPU  
6.1  
Features  
8/16-bit high performance AVR RISC Architecture  
– 138 instructions  
– Hardware multiplier  
32x8-bit registers directly connected to the ALU  
Stack in RAM  
Stack Pointer accessible in I/O memory space  
Direct addressing of up to 16M bytes of program and data memory  
True 16/24-bit access to 16/24-bit I/O registers  
Support for 8-, 16- and 32-bit Arithmetic  
Configuration Change Protection of system critical features  
6.2  
Overview  
The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure cor-  
rect program execution. The CPU must therefore be able to access memories, perform  
calculations and control peripherals. Interrupt handling is described in a separate section. Figure  
6-1 on page 7 shows the CPU block diagram.  
Figure 6-1. CPU block diagram  
DATA BUS  
Flash  
Program  
Program  
Counter  
Memory  
32 x 8 General  
Purpose  
Registers  
Instruction  
Register  
OCD  
STATUS/  
CONTROL  
Instruction  
Decode  
Multiplier/  
DES  
ALU  
DATA BUS  
Peripheral  
Module 1  
Peripheral  
Module 2  
SRAM  
EEPROM  
PMIC  
The AVR uses a Harvard architecture - with separate memories and buses for program and  
data. Instructions in the program memory are executed with a single level pipeline. While one  
instruction is being executed, the next instruction is pre-fetched from the program memory.  
7
8068R–AVR–08/10  

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