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ATR0625-EK1 PDF预览

ATR0625-EK1

更新时间: 2024-02-26 01:52:54
品牌 Logo 应用领域
爱特美尔 - ATMEL 全球定位系统
页数 文件大小 规格书
26页 336K
描述
GPS Baseband Processor SuperSense

ATR0625-EK1 数据手册

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Features  
16-channel GPS Correlator  
– 8192 Search Bins with GPS Acquisition Accelerator  
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)  
– Time to First Fix: 34s (Cold Start)  
– Acquisition Sensitivity: –142 dBm  
– Tracking Sensitivity: –158 dBm  
Utilizes the ARM7TDMI® ARM® Thumb® Processor Core  
– High-performance 32-bit RISC Architecture  
– High-density 16-bit Instruction Set  
GPS Baseband  
Processor  
SuperSense  
– Embedded ICE (In-circuit Emulator)  
128 Kbyte Internal RAM  
384 Kbyte Internal ROM with u-blox GPS Firmware  
6-channel Peripheral Data Controller (PDC)  
8-level Priority, Individually Maskable, Vectored Interrupt Controller  
– 2 External Interrupts  
ATR0625  
24 User-programmable I/O Lines  
1 USB Device Port  
– Universal Serial Bus (USB) V2.0 Full-speed Device  
– Embedded USB V2.0 Full-speed Transceiver  
– Suspend/Resume Logic  
Preliminary  
– Ping-pong Mode for Isochronous and Bulk Endpoints  
2 USARTs  
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART  
Master/Slave SPI Interface  
– 2 Dedicated Peripheral Data Controller (PDC) Channels  
– 8-bit to 16-bit Programmable Data Length  
– 4 External Slave Chip Selects  
Programmable Watchdog Timer  
Advanced Power Management Controller (APMC)  
– Peripherals Can Be Deactivated Individually  
– Geared Master Clock to Reduce Power Consumption  
– Sleep State with Disabled Master Clock  
– Hibernate State with 32.768 kHz Master Clock  
Real Time Clock (RTC)  
2.3V to 3.6V or 1.8V Core Supply Voltage  
Includes Power Supervisor  
1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance  
4 Kbytes Battery Backup Memory  
8 mm × 8 mm 56 Pin QFN56 Package  
Pb-free, RoHS-compliant, Green  
Rev. 4925A–GPS–02/06  

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