ATR0621P1
Table 3-1.
ATR0621P1 Pinout (Continued)
Pull Resistor
Pin Name LFBGA100
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OUT
IN
(Reset Value)(1) Firmware Label
PIO Bank A
“0”
PIO Bank B
P2
P3
G4
H5
A7
B1
A8
D2
G2
J8
Configurable (PD) BOOT_MODE
OH
NCS1
NCS1
NCS0
“0”
“0”
“0”
“0”
“0”
P4
OH
NCS0
P5
OH
NWE/NWR0
NOE/NRD
NUB/NWR1
STATUSLED
EXTINT0
NWE/NWR0
NOE/NRD
NUB/NWR1
“0”
P6
OH
P7
OH
P8
Configurable (PD)
PU to VBAT18
OH
P9
EXTINT0
EXTINT1
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
RF_ON
SIGHI0
SIGLO0
TCK
E4
H10
F3
EM_A0/NLB
EM_A21
EM_A0/NLB
NCS2
“0”
OH
EM_A21
Configurable (PU)
PU to VBAT18
Configurable (PD)
PD
GPSMODE2
GPSMODE3
NAADET1
ANTON
NPCS2
G10
J5
“0”
K5
E1
J4
Configurable (PU)
Configurable (PD)
Configurable (PU)
Configurable (PU)
Configurable (PD)
Configurable (PU)
PU to VBAT18
Configurable (PU)
Configurable (PU)
Configurable (PD)
NEEPROM
GPSMODE5
TXD1
SIGHI1
SCK1
NWD_OVF
SCK1
TXD1
K4
F1
“0”
“0”
GPSMODE6
TIMEPULSE
TXD2
SIGLO1
SCK2
H2
F2
SCK2
TXD2
TIMEPULSE
“0”
H8
H3
H1
D1
G8
E2
G1
E3
G5
H9
K6
F9
RXD2
RXD2
SCK
GPSMODE7
GPSMODE8
NAADET0
SCK
MOSI
MCLK_OUT
MOSI
MISO
NSS
“0”
“0”
“0”
MISO
Configurable (PU) GPSMODE10
Configurable (PU) GPSMODE11
NPCS0
NPCS1
NCS3
OH
EM_A20
EM_A20
“0”
Configurable (PU) GPSMODE12
NPCS3
AGCOUT0
PD
PU to VBAT18
PD
AGCOUT0
RXD1
RXD1
E10
J3
IN
IN
PU
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain
3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
5. This pin is not connected
7
4975BS–GPS–05/08