ATR0621P1
3. Pin Configuration
3.1
Pinout
Figure 3-1. Pinout LFBGA100 (Top View)
A B C D E F G H J K
10
9
8
7
6
5
4
3
2
1
ATR0621P1
Table 3-1.
ATR0621P1 Pinout
Pull Resistor
Pin Name LFBGA100
Pin Type
IN
(Reset Value)(1) Firmware Label
PIO Bank A
PIO Bank B
CLK23
DBG_EN
EM_A1
EM_A2
EM_A3
EM_A4
EM_A5
EM_A6
EM_A7
EM_A8
EM_A9
EM_A10
EM_A11
EM_A12
EM_A13
EM_A14
EM_A15
G9
H4
A6
A5
A4
A2
A3
B5
B4
B2
D4
C2
D6
D7
C3
C1
D5
IN
PD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain
3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
5. This pin is not connected
5
4975BS–GPS–05/08