Datasheet > ATL60/40

ATL60/40

更新时间： 2024-11-06 23:33:07

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
14页	112K
描述
FPGA

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ATL60/40 数据手册

Features

• 0.6 µm Drawn Gate Length (0.5 µm Leff) Sea-of-Gates Architecture

with Triple-level Metal

• 5.0V, 3.3V and 2.0V Operation including Mixed Voltages

• On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and

Manage Chip-to-Chip Clock Skew

• Compiled (Gate Level) and Embedded (Custom) SRAMs, ROM, and CAMs Available

• PCI, SCSI and High Speed (250 MHz) Buffers Available

• Easy Alternative Sourcing of Existing ASIC, FPGA and PLD Designs

• Design-for-Test Methods, Including JTAG, Serial and Boundary Scan and ATPG

• High Output Drive Capability: Up to 48 mA with Slew Rate Control

ASIC

Description

ATL 60 and

ATLS60 Series

Atmel’s next generation ATL60 Series CMOS ASICs are fabricated using a 0.6µm

drawn gate, oxide isolated, triple-level metal process. Extensive cell libraries are avail-

able and support the major CAD software tools. As with all Atmel ASIC families,

customer involvement and satisfaction is integral to all steps of the design flow. A vari-

ety of Design for Testability techniques are supported by the libraries, and a wide

range of packaging options are available. The ATLS version utilizes a fine pitch stag-

gered row on bond pads to achieve the smallest die size possible for a given pad

count. The ATLS60 is only available in a limited number of PQFP packages.

Table 1. ATL60 Array Organization

Device

Number

Raw

Gates

Routable

Gates

Max Pin

Count

Max I/O

Pins

Gate⁽¹⁾

Speed

ATL60/4

ATL60/15

ATL60/25

ATL60/40

ATL60/60

ATL60/85

ATL60/110

ATL60/150

ATL60/200

ATL60/235

ATL60/300

ATL60/435

ATL60/550

ATL60/700

ATL60/870

ATL60/1100

4,000

15,000

3,000

10,000

16,900

25,400

34,600

51,900

65,900

89,300

116,900

139,500

181,000

260,000

288,000

363,000

456,000

590,000

200 ps

25,000

38,000

100

120

144

160

184

208

226

256

304

340

380

424

480

58,000

112

136

152

176

200

218

248

296

332

372

416

472

86,000

110,000

149,000

195,000

232,000

301,000

430,000

545,000

693,000

870,000

1,119,000

Note:

1. Nominal two input NAND gate with a fanout of 2 at 5.0 volts

Rev. 0388D–ASIC–07/02

12 3 4 5 6 7...14

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